THE DESIGN OF BALANCED AMPLIFIER BASED ON COMMON-MODE FEEDBACK

The balanced operational amplifier including its merits and designing methods is discussed by comparing its performance to a conventional differential output amplifier when used in a single balanced stage. A balanced OTA circuit design is also presented.

Realization of Fully Differential Fourth-Order Bessel Filter with Accurate Group Delay

A fully differential R-MOSFET-C fourth-order Bessel active lowpass filter employing fully differential operational amplifier,passive resistors,and current-steering MOS transistors as a variable resistor is proposed.This proposed implementation relies on the tunability of current-steering MOS transistors operating in the triode region counteracting the concert deviation of resistor in the integrated circuit manufacturing technology in orde r that the group delay of Bessel active filter could be designed accurately.The amplifier is not only with voltage common-mode negative feedback,but also with current common-mode negative feedback,which will benefit for the stability of its D C operating point.0.75μs group delay fourth-order Bessel lowpass filter,whic h is synthesized according to passive doubly terminated RLC prototype lowpass filter,demonstrates better than -65dB THD using 100kHz,2.5V pp signal in Taiwan UMC 2P2M(2-poly,2-metal)5.0V,0.5μm CMOS technology.

An Ultra Low-Voltage and Low-Power OTA Using Bulk-Input Technique and Its Application in Active-RC Filters

This paper presents the design of a two-stage bulk-input pseudo-differential operational transconductance amplifier (OTA) and its application in active-RC filters. The OTA was designed in 90 nm CMOS process and operates at a single supply voltage of 0.5 V. Using a two-path bulk-driven OTA by the combination of two different amplifiers the DC gain and speed of the OTA is increased. Rail-to-rail input is made possible using the transistor’s bulk terminal as in input. Also a Miller-Feed-forward (MFF) compensation is utilized which is improved the gain bandwidth (GBW) and phase margin of the OTA. In addition, a new merged cross-coupled self-cascode pair is used that can provide higher gain. Also, a novel cost-effective bulk-input common-mode feedback (CMFB) circuit has been designed. Simplicity and ability of using this new merged CMFB circuit is superior compared with state-of-the-art CMFBs. The OTA has a 70.2 dB DC gain, a 2.5 MHz GBW and a 70.8o phase margin for a 20 PF capacitive load whereas consumes only 25 μw. Finally, an 8th order Butterworth active Biquadrate RC filter has been designed and this OTA was checked by a typical switched-capacitor (SC) integrator with a 1 MHz clock-frequency.

Design and noise analysis of a fully-differential charge pump for phase-locked loops

A fully-differential charge pump（FDCP）with perfect current matching and low output current noise is realized for phase-locked loops（PLLs）.An easily stable common-mode feedback（CMFB）circuit which can handle high input voltage swing is proposed.Current mismatch and current noise contribution from the CMFB circuit is minimized.In order to optimize PLL phase noise,the output current noise of the FDCP is analyzed in detail and calculated with the sampling principle.The calculation result agrees well with the simulation.Based on the noise analysis,many methods to lower output current noise of the FDCP are discussed.The fully-differential charge pump is integrated into a 1–2 GHz frequency synthesizer and fabricated in an SMIC CMOS 0.18μm process.The measured output reference spur is–64 dBc to–69 dBc.The in-band and out-band phase noise is–95 dBc/Hz at 3 kHz frequency offset and–123 dBc/Hz at 1 MHz frequency offset respectively.

A novel 2.2 Gbps LVDS driver circuit design based on 0.35μm CMOS

This paper presents a novel high-speed low voltage differential signaling （LVDS） driver design for pointto-point communication. The switching noise of the driver was greatly suppressed by adding a charge/discharge circuit and the operating frequency of the circuit was also increased. A simple and effective common-mode feedback circuit was added to stabilize the output common-mode voltage. The proposed driver was implemented in a standard 0.35 μm CMOS process with a die area of 0.15 mm^2. The test result shows that the proposed driver works well at 2.2 Gbps with power consumption of only 23 mW and 21.35 ps peak-to-peak jitter under a 1.8 V power supply.