Noise-induced bistable switching dynamics through a potential energy landscape

Interlinked positive feedback loops,an important building block of biochemical systems,can induce bistable switching,leading to long-lasting state changes by brief stimuli.In this work,prevalent mutual activation between two species as another positive feedback is added to a generic interlinked positive-feedback-loop model originating from many realistic biological circuits.A stochastic fluctuation of the positive feedback strength is introduced in a bistable interval of the feedback strength,and bistability appears for the moderate feedback strength at a certain noise level.Stability analysis based on the potential energy landscape is further utilized to explore the noise-induced switching behavior of two stable steady states.

A 3.3 kV 4H-SiC split gate MOSFET with a central implant region for superior trade-off between static and switching performance

A split gate MOSFET(SG-MOSFET)is widely known for reducing the reverse transfer capacitance(C_(RSS)).In a 3.3 kV class,the SG-MOSFET does not provide reliable operation due to the high gate oxide electric field.In addition to the poor static performance,the SG-MOSFET has issues such as the punch through and drain-induced barrier lowering(DIBL)caused by the high gate oxide electric field.As such,a 3.3 kV 4 H-SiC split gate MOSFET with a grounded central implant region(SG-CIMOSFET)is proposed to resolve these issues and for achieving a superior trade-off between the static and switching performance.The SG-CIMOSFET has a significantly low on-resistance(R_(ON))and maximum gate oxide field(E_(OX))due to the central implant region.A grounded central implant region significantly reduces the C_(RSS)and gate drain charge(Q_(GD))by partially screening the gate-to-drain capacitive coupling.Compared to a planar MOSFET,the SG MOSFET,central implant MOSFET(CIMOSFET),the SGCIMOSFET improve the R_(ON)×Q_(GD)by 83.7%,72.4%and 44.5%,respectively.The results show that the device features not only the smallest switching energy loss but also the fastest switching time.

A 4H-SiC trench MOSFET structure with wrap N-type pillar for low oxide field and enhanced switching performance

An optimized silicon carbide(SiC)trench metal-oxide-semiconductor field-effect transistor(MOSFET)structure with side-wall p-type pillar(p-pillar)and wrap n-type pillar(n-pillar)in the n-drain was investigated by utilizing Silvaco TCAD simulations.The optimized structure mainly includes a p+buried region,a light n-type current spreading layer(CSL),a p-type pillar region,and a wrapping n-type pillar region at the right and bottom of the p-pillar.The improved structure is named as SNPPT-MOS.The side-wall p-pillar region could better relieve the high electric field around the p+shielding region and the gate oxide in the off-state mode.The wrapping n-pillar region and CSL can also effectively reduce the specific on-resistance(Ron,sp).As a result,the SNPPT-MOS structure exhibits that the figure of merit(Fo M)related to the breakdown voltage(V_(BR))and Ron,sp(V_(BR)^2R_(on,sp))of the SNPPT-MOS is improved by 44.5%,in comparison to that of the conventional trench gate SJ MOSFET(full-SJ-MOS).In addition,the SNPPT-MOS structure achieves a much fasterwitching speed than the full-SJ-MOS,and the result indicates an appreciable reduction in the switching energy loss.

An Energy-Efficient 12b 2.56 MS/s SAR ADC Using Successive Scaling of Reference Voltages

This paper presents an energy efficient architecture for successive approximation register(SAR)analog to digital converter(ADC).SAR ADCs with a capacitor array structure have been widely used because of its simple architecture and relatively high speed.However,conventional SAR ADCs consume relatively high energy due to the large number of capacitors used in the capacitor array and their sizes scaled up along with the number of bits.The proposed architecture reduces the energy consumption as well as the capacitor size by employing a new array architecture that scales down the reference voltages instead of scaling up the capacitor sizes.The proposed 12-bit SAR ADC is implemented in Complementary Metal Oxide Semiconductor(CMOS)0.13 um library using Cadence Virtuoso design tool.Simulation results and mathematical model demonstrate the overall energy savings of up to 97.3%compared with conventional SAR ADC,67%compared with the SAR ADC with split capacitor,and 35%compared with the resistor and capacitor(R&C)Hybrid SAR ADC.The ADC achieves an effective number of bits(ENOB)of 11.27 bits and consumes 61.7 uW at sampling rate of 2.56 MS/s,offering an energy consumption of 9.8 fJ per conversion step.The proposed SAR ADC offers 95.5%reduction in chip core area compared to conventional architecture,while occupying an active area of 0.088 mm2.

Electrode Erosion of a High Energy Impulse Spark Gap Switch

Based on the principle of thermal conduction, three metal alloys （stainless steel, copper-tungsten and graphite） were chosen as the material of the high impulse current discharging switch. Experimental results indicate that the mass loss and surface erosion morphology of the electrode are related with the electrode material （conductivity σ, melting point Tin, density p and thermal capacity c） and the impulse transferred charge （or energy） per impulse for the same total impulse transferred charge. The experimental results indicate that the mass loss of stainless steel, copper-tungsten and graphite are 380.10 μg/C, 118.10 μg/C and 81.90 μg/C respectively under the condition of a total impulse transferred charge of 525 C and a transferred charge per impulse of 10.5 C. Under the same impulse transferred charge, the mass loss of copper-tungsten（118.10 μg/C） with the transferred charge per impulse at 10.5 C is far larger than the mass loss （38.61μg/C） at a 1.48 C transferred charge per impulse. The electrode erosion mechanism under high energy impulse arcs is analyzed briefly and it is suggested that by selecting high conductive metal or metal alloy as the electrode material of a high energy impulse spark gap switch and setting high erosion resistance material at the top of the electrode, the mass loss of the electrode can be reduced and the life of the switch prolonged.

Improved 4H-SiC UMOSFET with super-junction shield region

This article investigates an improved 4H-SiC trench gate metal–oxide–semiconductor field-effect transistor(MOSFET)(UMOSFET)fitted with a super-junction(SJ)shielded region.The modified structure is composed of two n-type conductive pillars,three p-type conductive pillars,an oxide trench under the gate,and a light n-type current spreading layer(NCSL)under the p-body.The n-type conductive pillars and the light n-type current spreading layer provide two paths to and promote the diffusion of a transverse current in the epitaxial layer,thus improving the specific on-resistance(R_(on,sp)).There are three p-type pillars in the modified structure,with the p-type pillars on both sides playing the same role.The p-type conductive pillars relieve the electric field(E-field)in the corner of the trench bottom.Two-dimensional simulation(silvaco TCAD)indicates that Ron,sp of the modified structure,and breakdown voltage(V_(BR))are improved by 22.2%and 21.1%respectively,while the maximum figure of merit(FOM=V_(BR)^(2)/R_(on,sp)) is improved by 79.0%.Furthermore,the improved structure achieves a light smaller low gate-to-drain charge(Q_(gd))and when compared with the conventional UMOSFET(conventional-UMOS),it displays great advantages for reducing the switching energy loss.These advantages are due to the fact that the p-type conductive pillars and n-type conductive pillars configured under the gate provide a substantial charge balance,which also enables the charge carriers to be extracted quickly.In the end,under the condition of the same total charge quantity,the simulation comparison of gate charge and OFF-state characteristics between Gaussdoped structure and uniform-doped structure shows that Gauss-doped structure increases the V_(BR)of the device without degradation of dynamic performance.

A 4H-SiC semi-super-junction shielded trench MOSFET: p-pillar is grounded to optimize the electric field characteristics

A 4H-SiC trench gate metal-oxide-semiconductor field-effect transistor(UMOSFET)with semi-super-junction shiel-ded structure(SS-UMOS)is proposed and compared with conventional trench MOSFET(CT-UMOS)in this work.The advantage of the proposed structure is given by comprehensive study of the mechanism of the local semi-super-junction structure at the bottom of the trench MOSFET.In particular,the influence of the bias condition of the p-pillar at the bottom of the trench on the static and dynamic performances of the device is compared and revealed.The on-resistance of SS-UMOS with grounded(G)and ungrounded(NG)p-pillar is reduced by 52%(G)and 71%(NG)compared to CT-UMOS,respectively.Additionally,gate ox-ide in the GSS-UMOS is fully protected by the p-shield layer as well as semi-super-junction structure under the trench and p-base regions.Thus,a reduced electric-field of 2 MV/cm can be achieved at the corner of the p-shield layer.However,the quasi-intrinsic protective layer cannot be formed in NGSS-UMOS due to the charge storage effect in the floating p-pillar,resulting in a large electric field of 2.7 MV/cm at the gate oxide layer.Moreover,the total switching loss of GSS-UMOS is 1.95 mJ/cm2 and is reduced by 18%compared with CT-UMOS.On the contrary,the NGSS-UMOS has the slowest overall switching speed due to the weakened shielding effect of the p-pillar and the largest gate-to-drain capacitance among the three.The proposed GSS-UMOS plays an important role in high-voltage and high-frequency applications,and will provide a valuable idea for device design and circuit applications.

An energy-efficient and highly linear switching capacitor procedure for SAR ADCs

An energy-efficient and highly linear capacitor switching procedure for successive approximation regis- ter （SAR） ADCs is presented. The proposed switching procedure achieves 37% less switching energy when compared to the well-known VcM-based switching scheme. Moreover, the proposed method shows better linearity than the VcM-based one. The proposed switching procedure is applied to a 10-bit 1.0 V 300 kS/s SAR ADC implemented in 0.18μm standard CMOS. The measured results show the SAR ADC achieves an SNDR of 55.48 dB, SFDR of 66.98 dB, and consumes 2.13 μW at a 1.0 V power supply, resulting in a figure-of-merit of 14.66 fJ/conversion- step. The measured peak DNL and 1NL are 0.52/-0.47 LSB and 0.72/-0.79 LSB, respectively, and the peak INL 1 is observed at 4^-1 VFS and 4^-3 VFS, the same as the static nonlinearity model.

On the State-dependent Switched Energy Functions of DFIG-based Wind Power Generation Systems

This paper proposes a novel state-dependent switched energy function(SdSEF)for general nonlinear autonomous systems,and constructs an SdSEF for doubly-fed induction generator(DFIG)-based wind power generation systems(WPGSs).Different from the conventional energy function,SdSEF is a piece-wise continuous function,and it satisfies the conditions of conventional energy functions on each of its continuous segments.SdSEF is designed to bridge the gap between the well-developed energy function theory and the description of system energy of complex nonlinear systems,such as power electronics converter systems.The stability criterion of nonlinear autonomous systems is investigated with SdSEF,and mathematical proof is presented.The SdSEF of a typical DFIGbased WPGS is simulated in the whole processes of a grid fault and fault recovery.Simulation results verify the negativeness of the derivative of each continuous segment of the SdSEF.