A New Switching Sequences of SVPWM for Six-Phase Induction Motor with Features of Reduced Switching Losses

In this paper,new SVPWM switching sequences for six-phase asymmetrical induction motor drives are derived with the aim to reduce inverter’s switching losses.Total three switching sequences are introduced in this paper.These sequences are derived such that the phases get continuously clamped when a current of the phases is around its peak magnitude and hence reduced switching losses are recorded.The comparative performances of these modulation techniques are studied with two existing switching sequences.Simulation,analytical and experimental results are presented.Based on these results,it is found that new switching sequences reduce switching losses effectively in dual three phase inverters.

Low switching loss and increased short-circuit capability split-gate SiC trench MOSFET with p-type pillar

A split-gate SiC trench gate MOSFET with stepped thick oxide, source-connected split-gate(SG), and p-type pillar(ppillar) surrounded thick oxide shielding region(GSDP-TMOS) is investigated by Silvaco TCAD simulations. The sourceconnected SG region and p-pillar shielding region are introduced to form an effective two-level shielding, which reduces the specific gate–drain charge(Q_(gd,sp)) and the saturation current, thus reducing the switching loss and increasing the short-circuit capability. The thick oxide that surrounds a p-pillar shielding region efficiently protects gate oxide from being damaged by peaked electric field, thereby increasing the breakdown voltage(BV). Additionally, because of the high concentration in the n-type drift region, the electrons diffuse rapidly and the specific on-resistance(Ron,sp) becomes smaller.In the end, comparing with the bottom p~+ shielded trench MOSFET(GP-TMOS), the Baliga figure of merit(BFOM,BV~2/R_(on,sp)) is increased by 169.6%, and the high-frequency figure of merit(HF-FOM, R_(on,sp) × Q_(gd,sp)) is improved by310%, respectively.

A 3.3 kV 4H-SiC split gate MOSFET with a central implant region for superior trade-off between static and switching performance

A split gate MOSFET(SG-MOSFET)is widely known for reducing the reverse transfer capacitance(C_(RSS)).In a 3.3 kV class,the SG-MOSFET does not provide reliable operation due to the high gate oxide electric field.In addition to the poor static performance,the SG-MOSFET has issues such as the punch through and drain-induced barrier lowering(DIBL)caused by the high gate oxide electric field.As such,a 3.3 kV 4 H-SiC split gate MOSFET with a grounded central implant region(SG-CIMOSFET)is proposed to resolve these issues and for achieving a superior trade-off between the static and switching performance.The SG-CIMOSFET has a significantly low on-resistance(R_(ON))and maximum gate oxide field(E_(OX))due to the central implant region.A grounded central implant region significantly reduces the C_(RSS)and gate drain charge(Q_(GD))by partially screening the gate-to-drain capacitive coupling.Compared to a planar MOSFET,the SG MOSFET,central implant MOSFET(CIMOSFET),the SGCIMOSFET improve the R_(ON)×Q_(GD)by 83.7%,72.4%and 44.5%,respectively.The results show that the device features not only the smallest switching energy loss but also the fastest switching time.

A 4H-SiC trench MOSFET structure with wrap N-type pillar for low oxide field and enhanced switching performance

An optimized silicon carbide(SiC)trench metal-oxide-semiconductor field-effect transistor(MOSFET)structure with side-wall p-type pillar(p-pillar)and wrap n-type pillar(n-pillar)in the n-drain was investigated by utilizing Silvaco TCAD simulations.The optimized structure mainly includes a p+buried region,a light n-type current spreading layer(CSL),a p-type pillar region,and a wrapping n-type pillar region at the right and bottom of the p-pillar.The improved structure is named as SNPPT-MOS.The side-wall p-pillar region could better relieve the high electric field around the p+shielding region and the gate oxide in the off-state mode.The wrapping n-pillar region and CSL can also effectively reduce the specific on-resistance(Ron,sp).As a result,the SNPPT-MOS structure exhibits that the figure of merit(Fo M)related to the breakdown voltage(V_(BR))and Ron,sp(V_(BR)^2R_(on,sp))of the SNPPT-MOS is improved by 44.5%,in comparison to that of the conventional trench gate SJ MOSFET(full-SJ-MOS).In addition,the SNPPT-MOS structure achieves a much fasterwitching speed than the full-SJ-MOS,and the result indicates an appreciable reduction in the switching energy loss.

Low working loss Si/4H-SiC heterojunction MOSFET with analysis of the gate-controlled tunneling effect

A silicon (Si)/silicon carbide (4H-SiC) heterojunction double-trench metal-oxide-semiconductor field effect transistor (MOSFET) (HDT-MOS) with the gate-controlled tunneling effect is proposed for the first time based on simulations. In this structure, the channel regions are made of Si to take advantage of its high channel mobility and carrier density. The voltage-withstanding region is made of 4H-SiC so that HDT-MOS has a high breakdown voltage (BV) similar to pure 4H-SiC double-trench MOSFETs (DT-MOSs). The gate-controlled tunneling effect indicates that the gate voltage (V_(G)) has a remarkable influence on the tunneling current of the heterojunction. The accumulation layer formed with positive VG can reduce the width of the Si/SiC heterointerface barrier, similar to the heavily doped region in an Ohmic contact. This narrower barrier is easier for electrons to tunnel through, resulting in a lower heterointerface resistance. Thus, with similar BV (approximately 1770 V), the specific on-state resistance (R_(ON-SP)) of HDT-MOS is reduced by 0.77 mΩ·cm^(2) compared with that of DT-MOS. The gate-to-drain charge (Q_(GD)) and switching loss of HDT-MOS are 52.14% and 22.59% lower than those of DT-MOS, respectively, due to the lower gate platform voltage (V_(GP)) and the corresponding smaller variation (ΔV_(GP)). The figure of merit (Q_(GD)×R_(ON-SP)) of HDT-MOS decreases by 61.25%. Moreover, the heterointerface charges can reduce RON-SP of HDT-MOS due to trap-assisted tunneling while the heterointerface traps show the opposite effect. Therefore, the HDT-MOS structure can significantly reduce the working loss of SiC MOSFET, leading to a lower temperature rise when the devices are applied in the system.

IC Pattern Based Power Factor Maximization Model for Improved Power Stabilization

The voltagefluctuation in electric circuits has been identified as key issue in different electric systems.As the usage of electricity growing in rapid way,there exist higherfluctuations in powerflow.To maintain theflow or stabi-lity of power in any electric circuit,there are many circuit models are discussed in literature.However,they suffer to maintain the output voltage and not capable of maintaining power stability.To improve the performance in power stabilization,an efficient IC pattern based power factor maximization model(ICPFMM)in this article.The model is focused on improving the power stability with the use of IC(Inductor and Conductor)towards identifying most efficient circuit for the current duty cycle according to the input voltage,voltage in capacitor and output voltage required.The model with boost converter diverts the incoming voltage through number of conductors and inductors.By triggering specific inductor,a specific capacitor gets charged and a particular circuit gets on.The model maintains num-ber of IC(Inductor and Conductor)patterns through which the powerflow occurs.According to that,the pattern available,the mofset controls the level of power to be regulated through any circuit.From the pattern,the model computes the Cir-cuits Switching Loss and Circuits Conduction Loss for various circuits.Accord-ing to the input voltage,the model estimates Circuit Power Stabilization Support(CPSS)according to the voltage available in any capacitor and input voltage.Using the value of CPSS,the model trigger optimal number of circuits to maintain voltage stability.In this approach,more than one circuit has been triggered to maintain output voltage and to get charged.The proposed model not only main-tains power stability but also reduces the wastage in voltage which is not utilized.The proposed model improves the performance in voltage stability with less switching loss.

SiC trench MOSFET with dual shield gate and optimized JFET layer for improved dynamic performance and safe operating area capability

A novel silicon carbide(SiC) trench metal–oxide–semiconductor field-effect transistor(MOSFET) with a dual shield gate(DSG) and optimized junction field-effect transistor(JFET) layer(ODSG-TMOS) is proposed. The combination of the DSG and optimized JFET layer not only significantly improves the device’s dynamic performance but also greatly enhances the safe operating area(SOA). Numerical analysis is carried out with Silvaco TCAD to study the performance of the proposed structure. Simulation results show that comparing with the conventional asymmetric trench MOSFET(Con-ATMOS), the specific on-resistance(Ron,sp) is significantly reduced at almost the same avalanche breakdown voltage(BVav). Moreover, the DSG structure brings about much smaller reverse transfer capacitance(Crss) and input capacitance(Ciss), which helps to reduce the gate–drain charge(Qgd) and gate charge(Qg). Therefore, the high frequency figure of merit(HFFOM) of Ron,sp·Qgdand Ron,sp· Qgfor the proposed ODSG-TMOS are improved by 83.5% and 76.4%, respectively.The switching power loss of the proposed ODSG-TMOS is 77.0% lower than that of the Con-ATMOS. In addition, the SOA of the proposed device is also enhanced. The saturation drain current(Id,sat) at a gate voltage(Vgs) of 15 V for the ODSGTMOS is reduced by 17.2% owing to the JFET effect provided by the lower shield gate(SG) at a large drain voltage. With the reduced Id,sat, the short-circuit withstand time is improved by 87.5% compared with the Con-ATMOS. The large-current turn-off capability is also improved, which is important for the widely used inductive load applications.

Closed Loop Control of Bi-Directional Soft Switched Quasi Z-Source DC-DC Converter

Quasi Z-source converter is a single stage soft switched power converter derived from Z-source converter topology, employing an impedance network coupling the source with the converter. The quasi Z-source source converter can buck or boost the voltage and current flow is bidirectional. The duty cycle of the switch can be adjusted to maintain constant voltage during load change. To obtain constant output voltage, proper controller design is a must. This paper presents closed loop control of quasi Z-source converter using PI controller where controller parameters are estimated using the small signal model of the entire system. The transfer function of the system with AC sweep is used to obtain appropriate proportional and integral gain constants to reduce transient dynamics and to reduce steady state error.

3.3 kV 4H-SiC DMOSFET with a source-contacted dummy gate for high-frequency applications

In this paper,a 4 H-Si C DMOSFET with a source-contacted dummy gate(DG-MOSFET)is proposed and analyzed through Sentaurus TCAD and PSIM simulations.The source-contacted MOS structure forms fewer depletion regions than the PN junction.Therefore,the overlapping region between the gate and the drain can be significantly reduced while limiting RON degradation.As a result,the DG-MOSFET offers an improved high-frequency figure of merit(HF-FOM)over the conventional DMOSFET(C-MOSFET)and central-implant MOSFET(CI-MOSFET).The HF-FOM(RON×QGD)of the DG-MOSFET was improved by59.2%and 22.2%compared with those of the C-MOSFET and CI-MOSFET,respectively.In a double-pulse test,the DG-MOSFET could save total power losses of 53.4%and 5.51%,respectively.Moreover,in a power circuit simulation,the switching power loss was reduced by 61.9%and 12.7%in a buck converter and 61%and 9.6%in a boost converter.

Improved 4H-SiC UMOSFET with super-junction shield region

This article investigates an improved 4H-SiC trench gate metal–oxide–semiconductor field-effect transistor(MOSFET)(UMOSFET)fitted with a super-junction(SJ)shielded region.The modified structure is composed of two n-type conductive pillars,three p-type conductive pillars,an oxide trench under the gate,and a light n-type current spreading layer(NCSL)under the p-body.The n-type conductive pillars and the light n-type current spreading layer provide two paths to and promote the diffusion of a transverse current in the epitaxial layer,thus improving the specific on-resistance(R_(on,sp)).There are three p-type pillars in the modified structure,with the p-type pillars on both sides playing the same role.The p-type conductive pillars relieve the electric field(E-field)in the corner of the trench bottom.Two-dimensional simulation(silvaco TCAD)indicates that Ron,sp of the modified structure,and breakdown voltage(V_(BR))are improved by 22.2%and 21.1%respectively,while the maximum figure of merit(FOM=V_(BR)^(2)/R_(on,sp)) is improved by 79.0%.Furthermore,the improved structure achieves a light smaller low gate-to-drain charge(Q_(gd))and when compared with the conventional UMOSFET(conventional-UMOS),it displays great advantages for reducing the switching energy loss.These advantages are due to the fact that the p-type conductive pillars and n-type conductive pillars configured under the gate provide a substantial charge balance,which also enables the charge carriers to be extracted quickly.In the end,under the condition of the same total charge quantity,the simulation comparison of gate charge and OFF-state characteristics between Gaussdoped structure and uniform-doped structure shows that Gauss-doped structure increases the V_(BR)of the device without degradation of dynamic performance.

A 3D SiC MOSFET with poly-silicon/SiC heterojunction diode

A three-dimensional(3D)silicon-carbide(SiC)trench metal-oxide-semiconductor field-effect transistor(MOSFET)with a heterojunction diode(HJD-TMOS)is proposed and studied in this work.The SiC MOSFET is characterized by an HJD which is partially embedded on one side of the gate.When the device is in the turn-on state,the body parasitic diode can be effectively controlled by the embedded HJD,the switching loss thus decreases for the device.Moreover,a highly-doped P+layer is encircled the gate oxide on the same side as the HJD and under the gate oxide,which is used to lighten the electric field concentration and improve the reliability of gate oxide layer.Physical mechanism for the HJD-TMOS is analyzed.Comparing with the conventional device with the same level of on-resistance,the breakdown voltage of the HJD-TMOS is improved by 23.4%,and the miller charge and the switching loss decrease by 43.2%and 48.6%,respectively.

A 4H-SiC semi-super-junction shielded trench MOSFET: p-pillar is grounded to optimize the electric field characteristics

A 4H-SiC trench gate metal-oxide-semiconductor field-effect transistor(UMOSFET)with semi-super-junction shiel-ded structure(SS-UMOS)is proposed and compared with conventional trench MOSFET(CT-UMOS)in this work.The advantage of the proposed structure is given by comprehensive study of the mechanism of the local semi-super-junction structure at the bottom of the trench MOSFET.In particular,the influence of the bias condition of the p-pillar at the bottom of the trench on the static and dynamic performances of the device is compared and revealed.The on-resistance of SS-UMOS with grounded(G)and ungrounded(NG)p-pillar is reduced by 52%(G)and 71%(NG)compared to CT-UMOS,respectively.Additionally,gate ox-ide in the GSS-UMOS is fully protected by the p-shield layer as well as semi-super-junction structure under the trench and p-base regions.Thus,a reduced electric-field of 2 MV/cm can be achieved at the corner of the p-shield layer.However,the quasi-intrinsic protective layer cannot be formed in NGSS-UMOS due to the charge storage effect in the floating p-pillar,resulting in a large electric field of 2.7 MV/cm at the gate oxide layer.Moreover,the total switching loss of GSS-UMOS is 1.95 mJ/cm2 and is reduced by 18%compared with CT-UMOS.On the contrary,the NGSS-UMOS has the slowest overall switching speed due to the weakened shielding effect of the p-pillar and the largest gate-to-drain capacitance among the three.The proposed GSS-UMOS plays an important role in high-voltage and high-frequency applications,and will provide a valuable idea for device design and circuit applications.

Application of artificial neural network for switching loss modeling in power IGBTs

The modeling of switching loss in semiconductor power devices is important in practice for the prediction and evaluation of thermal safety and system reliability.Both simulation-based behavioral models and data processing-based empirical models are difficult and have limited applications.Although the artificial neural network(ANN) algorithm has often been used for modeling, it has never been used for modeling insulated gate bipolar transistor(IGBT) transient loss.In this paper, we attempt to use the ANN method for this purpose, using a customized switching loss test bench.We compare its performance with two conventional curve-fitting models and verify the results by experiment.Our model is generally superior in calculation speed, accuracy, and data requirement, and is also able to be extended to loss modeling for all kinds of semiconductor power devices.

Dual-frequency Discontinuous Space Vector Pulse Width Modulation for Five-phase Voltage Source Inverters with Harmonic Injection

This paper proposes a dual-frequency discontinuous space vector pulse width modulation(DFDSVPWM)for a five-phase voltage source inverter with harmonic injection.In this modulation,for dual-frequency voltage output and reduction of switching losses,two different zero-vector-inserted modes are flexibly employed by alternatively using two types of zero vectors.Based on the comparison with continuous SVPWM,the idea and principle of the proposed DFDSVPWM are analyzed and an example of PWM signals for one bridge is also presented.For switching losses analysis,the impact factors and the calculation method are investigated and the corresponding implementation is given as well.The simulation and experimental results from a prototype verify the correctness and effectiveness of the proposed modulation and it has the advantages of outputting dual-frequency voltage and reducing switching losses.

Fast valve power loss evaluation method for modular multi-level converter operating at high-frequency

There is no common accepted way for calculating the valve power loss of modular multilevel converter(MMC).Valve power loss estimation based on analytical calculation is inaccurate to address the switching power loss and valve power loss estimation based on detailed electro-magnetic simulation is of low speed.To solve this problem,a method of valve power loss estimation based on the detailed equivalent simulation model of MMC is proposed.Results of valve power loss analysis of 201-level 500MW MMC operating at 50Hz~1000Hz are presented.It is seen that the valve power loss of a MMC increased by 12,40 and 93%under 200Hz,500Hz and 1000Hz operating frequency.The article concludes that in a device with isolated inner AC system,MMC operating at higher frequency will be more competitive than typical 50Hz/60Hz MMC with moderate increase of operating power loss and significant reduction of the size of the AC components.