The theories of synchronization based on secure communications using digital chaos are presented. A new synchronous method-cycles-interval Pulse drive is developed and realized. Experimental results show it is availab...The theories of synchronization based on secure communications using digital chaos are presented. A new synchronous method-cycles-interval Pulse drive is developed and realized. Experimental results show it is available, and in order to reduce synchronous noise, a method using model references solves the ratio of signal power to noise power, so the secure communication system can be realized.展开更多
In recent years,as a promising way to realize digital transformation,digital twin shop-floor(DTS)plays an impor-tant role in smart manufacturing.The core feature of DTS is the synchronization.How to implement and main...In recent years,as a promising way to realize digital transformation,digital twin shop-floor(DTS)plays an impor-tant role in smart manufacturing.The core feature of DTS is the synchronization.How to implement and maintain the synchronization is critical for DTS.However,there is still a lack of a common definition for synchronization in DTS.Besides,a systematic synchronization mechanism for DTS is strongly needed.This paper first summarizes the defi-nition and requirements of synchronization in DTS,to clarify the understanding of synchronization in DTS.Then,a 5M synchronization mechanism for DTS is proposed,where 5M refers to multi-system data,multi-fidelity model,multi-resource state,multi-level state,and multi-stage operation.As a bottom-up synchronization mechanism,5M synchronization mechanism for DTS has the potential to support DTS to achieve and maintain physical-virtual state synchronization,and to realize operation synchronization of DTS.The implementation methods of 5M synchronization mechanism for DTS are also introduced.Finally,the proposed synchronization mechanism is validated in a digital twin satellite assembly shop-floor,which proves the effectiveness and feasibility of the mechanism.展开更多
The design of an FPGA（ field programmable gate array） based programmable SONET （synchronous optical network） OC-192 10 Gbit/s PRBS （pseudo-random binary sequence） generator and a bit interleaved polarity 8 （BI...The design of an FPGA（ field programmable gate array） based programmable SONET （synchronous optical network） OC-192 10 Gbit/s PRBS （pseudo-random binary sequence） generator and a bit interleaved polarity 8 （BIP-8） error detector is presented. Implemented in a parallel feedback configuration, this tester features PRBS generation of sequences with bit lengths of 2^7 - 1,2^10- 1,2^15 - 1,2^23 - land 2^31 - 1 for up to 10 Gbit/s applications with a 10 Gbit/s optical transceiver, via the SFI-4 （OC-192 serdes-framer interface）. In the OC-192 frame alignment circuit, a dichotomy search algorithm logic which performs the functions of word alignment and STM-64/OC192 de-frame speeds up the frame sync logic and reduces circuit complexity greatly. The system can be used as a low cost tester to evaluate the performance of OC-192 devices and components, taking the replacement of precious commercial PRBS testers.展开更多
The paper proposes a low power non-volatile baseband processor with wake-up identification(WUI) receiver for LR-WPAN transceiver.It consists of WUI receiver,main receiver,transmitter,non-volatile memory(NVM) and power...The paper proposes a low power non-volatile baseband processor with wake-up identification(WUI) receiver for LR-WPAN transceiver.It consists of WUI receiver,main receiver,transmitter,non-volatile memory(NVM) and power management module.The main receiver adopts a unified simplified synchronization method and channel codec with proactive Reed-Solomon Bypass technique,which increases the robustness and energy efficiency of receiver.The WUI receiver specifies the communication node and wakes up the transceiver to reduce average power consumption of the transceiver.The embedded NVM can backup/restore the states information of processor that avoids the loss of the state information caused by power failure and reduces the unnecessary power of repetitive computation when the processor is waked up from power down mode.The baseband processor is designed and verified on a FPGA board.The simulated power consumption of processor is 5.1uW for transmitting and 28.2μW for receiving.The WUI receiver technique reduces the average power consumption of transceiver remarkably.If the transceiver operates 30 seconds in every 15 minutes,the average power consumption of the transceiver can be reduced by two orders of magnitude.The NVM avoids the loss of the state information caused by power failure and energy waste caused by repetitive computation.展开更多
基金This work was financially supported by the National Nature Science Foundation of China (No. 69772014)
文摘The theories of synchronization based on secure communications using digital chaos are presented. A new synchronous method-cycles-interval Pulse drive is developed and realized. Experimental results show it is available, and in order to reduce synchronous noise, a method using model references solves the ratio of signal power to noise power, so the secure communication system can be realized.
基金Supported by National Natural Science Foundation of China(NSFC)(Grant Nos.52120105008,52005026,52005025).
文摘In recent years,as a promising way to realize digital transformation,digital twin shop-floor(DTS)plays an impor-tant role in smart manufacturing.The core feature of DTS is the synchronization.How to implement and maintain the synchronization is critical for DTS.However,there is still a lack of a common definition for synchronization in DTS.Besides,a systematic synchronization mechanism for DTS is strongly needed.This paper first summarizes the defi-nition and requirements of synchronization in DTS,to clarify the understanding of synchronization in DTS.Then,a 5M synchronization mechanism for DTS is proposed,where 5M refers to multi-system data,multi-fidelity model,multi-resource state,multi-level state,and multi-stage operation.As a bottom-up synchronization mechanism,5M synchronization mechanism for DTS has the potential to support DTS to achieve and maintain physical-virtual state synchronization,and to realize operation synchronization of DTS.The implementation methods of 5M synchronization mechanism for DTS are also introduced.Finally,the proposed synchronization mechanism is validated in a digital twin satellite assembly shop-floor,which proves the effectiveness and feasibility of the mechanism.
文摘The design of an FPGA（ field programmable gate array） based programmable SONET （synchronous optical network） OC-192 10 Gbit/s PRBS （pseudo-random binary sequence） generator and a bit interleaved polarity 8 （BIP-8） error detector is presented. Implemented in a parallel feedback configuration, this tester features PRBS generation of sequences with bit lengths of 2^7 - 1,2^10- 1,2^15 - 1,2^23 - land 2^31 - 1 for up to 10 Gbit/s applications with a 10 Gbit/s optical transceiver, via the SFI-4 （OC-192 serdes-framer interface）. In the OC-192 frame alignment circuit, a dichotomy search algorithm logic which performs the functions of word alignment and STM-64/OC192 de-frame speeds up the frame sync logic and reduces circuit complexity greatly. The system can be used as a low cost tester to evaluate the performance of OC-192 devices and components, taking the replacement of precious commercial PRBS testers.
基金supported in part by the National Natural Science Foundation of China(No.61306027)
文摘The paper proposes a low power non-volatile baseband processor with wake-up identification(WUI) receiver for LR-WPAN transceiver.It consists of WUI receiver,main receiver,transmitter,non-volatile memory(NVM) and power management module.The main receiver adopts a unified simplified synchronization method and channel codec with proactive Reed-Solomon Bypass technique,which increases the robustness and energy efficiency of receiver.The WUI receiver specifies the communication node and wakes up the transceiver to reduce average power consumption of the transceiver.The embedded NVM can backup/restore the states information of processor that avoids the loss of the state information caused by power failure and reduces the unnecessary power of repetitive computation when the processor is waked up from power down mode.The baseband processor is designed and verified on a FPGA board.The simulated power consumption of processor is 5.1uW for transmitting and 28.2μW for receiving.The WUI receiver technique reduces the average power consumption of transceiver remarkably.If the transceiver operates 30 seconds in every 15 minutes,the average power consumption of the transceiver can be reduced by two orders of magnitude.The NVM avoids the loss of the state information caused by power failure and energy waste caused by repetitive computation.
