There are varieties of embedded systems in the world. It is a big challenge to optimize the instruction sets of System on Chips (SoCs) according to different systems' working environments. The idea of programmable...There are varieties of embedded systems in the world. It is a big challenge to optimize the instruction sets of System on Chips (SoCs) according to different systems' working environments. The idea of programmable instruction set is an effective method to gain embedded system's re-configurability. This letter presents a logic module for Java processor to be capable of using programmable instruction set. Cost (area, power, and timing) of the module is trivial. Such module is also reusable for other embedded system solutions besides Java systems.展开更多
针对三冗余机电静压伺服系统的研制需求,设计了基于双核全可编程片上系统(All Programmable System on Chip,APSoC)技术的多总线三冗余伺服控制驱动器。通过数字总线实现子控制驱动模块之间信息共享,采用IP核技术实现硬件加速、多电机...针对三冗余机电静压伺服系统的研制需求,设计了基于双核全可编程片上系统(All Programmable System on Chip,APSoC)技术的多总线三冗余伺服控制驱动器。通过数字总线实现子控制驱动模块之间信息共享,采用IP核技术实现硬件加速、多电机高速并行控制;通过试验验证多电机控制的同步性能和测量细节全还原技术;采用多种温度、压力传感器、过流保护电路等构建伺服系统健康网络体系,结合余度表决和故障切除逻辑搭建了三冗余控制驱动平台,对多任务的不同实时性需求分配任务等级,双核协同工作,研制的产品实物通过了系统验证。展开更多
A memory and driving clock efficient design scheme to achieve WCDMA high-speed channel decoder on a single XILINX’ XVC1000E FPGA chip is presented. Using a modified MAP algorithm, say parallel Sliding Window logarith...A memory and driving clock efficient design scheme to achieve WCDMA high-speed channel decoder on a single XILINX’ XVC1000E FPGA chip is presented. Using a modified MAP algorithm, say parallel Sliding Window logarithmic Maximum A Posterior (PSW-log-MAP), the on-chip turbo decoder can decode an information bit by only an average of two clocks per iteration. On the other hand, a high-parallel pipeline Viterbi algorithm is adopted to realize the 256-state convolutional code decoding. The final decoder with an 8×chip-clock (30 72MHz) driving can concurrently process a data rate up to 2 5Mbps of turbo coded sequences and a data rate over 400kbps of convolutional codes. There is no extern memory needed. Test results show that the decoding performance is only 0 2～0 3dB or less lost comparing to float simulation.展开更多
基金Supported by the Guangzhou Key Technology R&D Program (No.2007Z2-D0011)
文摘There are varieties of embedded systems in the world. It is a big challenge to optimize the instruction sets of System on Chips (SoCs) according to different systems' working environments. The idea of programmable instruction set is an effective method to gain embedded system's re-configurability. This letter presents a logic module for Java processor to be capable of using programmable instruction set. Cost (area, power, and timing) of the module is trivial. Such module is also reusable for other embedded system solutions besides Java systems.
文摘针对三冗余机电静压伺服系统的研制需求,设计了基于双核全可编程片上系统(All Programmable System on Chip,APSoC)技术的多总线三冗余伺服控制驱动器。通过数字总线实现子控制驱动模块之间信息共享,采用IP核技术实现硬件加速、多电机高速并行控制;通过试验验证多电机控制的同步性能和测量细节全还原技术;采用多种温度、压力传感器、过流保护电路等构建伺服系统健康网络体系,结合余度表决和故障切除逻辑搭建了三冗余控制驱动平台,对多任务的不同实时性需求分配任务等级,双核协同工作,研制的产品实物通过了系统验证。
文摘A memory and driving clock efficient design scheme to achieve WCDMA high-speed channel decoder on a single XILINX’ XVC1000E FPGA chip is presented. Using a modified MAP algorithm, say parallel Sliding Window logarithmic Maximum A Posterior (PSW-log-MAP), the on-chip turbo decoder can decode an information bit by only an average of two clocks per iteration. On the other hand, a high-parallel pipeline Viterbi algorithm is adopted to realize the 256-state convolutional code decoding. The final decoder with an 8×chip-clock (30 72MHz) driving can concurrently process a data rate up to 2 5Mbps of turbo coded sequences and a data rate over 400kbps of convolutional codes. There is no extern memory needed. Test results show that the decoding performance is only 0 2～0 3dB or less lost comparing to float simulation.
