Challenges to Data-Path Physical Design Inside SOC

Previously,a single data-path stack was adequate for data-path chips,and the complexity and size of the data-path was comparatively small.As current data-path chips,such as system-on-a-chip (SOC),become more complex,multiple data-path stacks are required to implement the entire data-path.As more data-path stacks are integrated into SOC,data-path is becoming a critical part of the whole giga-scale integrated circuits (GSI) design.The traditional physical design methodology can not satisfy the data-path performance requirements,because it can not accommodate the data-path bit-sliced structure and the strict performance (such as timing,coupling,and crosstalk) constraints.Challenges in the data-path physical design are addressed.The fundamental problems and key technologies in data-path physical design are analysed.The corresponding researches and solutions in this research field are also discussed.

An Efficient Test Data Compression Technique Based on Codes

This paper presents a new test data compression/decompression method for SoC testing,called hybrid run length codes. The method makes a full analysis of the factors which influence test parameters：compression ratio,test application time, and area overhead. To improve the compression ratio, the new method is based on variable-to-variable run length codes,and a novel algorithm is proposed to reorder the test vectors and fill the unspecified bits in the pre-processing step. With a novel on-chip decoder, low test application time and low area overhead are obtained by hybrid run length codes. Finally, an experimental comparison on ISCAS 89 benchmark circuits validates the proposed method

用于SOC测试的一种有效的BIST方法

为了提高SOC芯片的可测性和可靠性,我们提出了一种SOC测试的BIST技术的实现方案.针对某所自行研制的数字模拟混合信号SOC芯片,我们使用了不同的可测性技术.比如对模拟模块使用改进的BIST方法,对嵌入式存储器使用了MBIST技术.一系列的测试实验数据表明,该BIST方法能有效提高测试覆盖率.

Hardware-Software Co-Simulation for SOC Functional Verification

A hardware-software co-simulation method for system on chip (SOC) design is discussed. It is based on an instruction set simulator (ISS) and an event-driven hardware simulator, and a bus interface model that is described in C language provides the interface between the two. The bus interface model and the ISS are linked into a singleton program--the software simulator, which communicate with the hardware simulator through Windows sockets. The implementation of the bus interface model and the synchronization between hardware and software simulator are discussed in detail. Co-simulation control of the hardware simulator is also discussed.

Test Resource Partitioning Based on Efficient Response Compaction for Test Time and Tester Channels Reduction

This paper presents a test resource partitioning technique based on anefficient response compaction design called quotient compactor(q-Compactor). Because q-Compactor isa single-output compactor, high compaction ratios can be obtained even for chips with a small numberof outputs. Some theorems for the design of q-Compactor are presented to achieve full diagnosticability, minimize error cancellation and handle unknown bits in the outputs of the circuit undertest (CUT). The q-Compactor can also be moved to the load-board, so as to compact the outputresponse of the CUT even during functional testing. Therefore, the number of tester channelsrequired to test the chip is significantly reduced. The experimental results on the ISCAS ''89benchmark circuits and an MPEG 2 decoder SoC show that the proposed compaction scheme is veryefficient.

An attack-immune trusted architecture for supervisory aircraft hardware

With the wide application of electronic hardware in aircraft such as air-to-ground communication,satellite communication,positioning system and so on,aircraft hardware is facing great secure pressure.Focusing on the secure problem of aircraft hardware,this paper proposes a supervisory control architecture based on secure System-on-a-Chip(So C)system.The proposed architecture is attack-immune and trustworthy,which can support trusted escrow application and Dynamic Integrity Measurement(DIM)without interference.This architecture is characterized by a Trusted Monitoring System(TMS)hardware isolated from the Main Processor System(MPS),a secure access channel from TMS to the running memory of the MPS,and the channel is unidirectional.Based on this architecture,the DIM program running on TMS is used to measure and call the Lightweight Measurement Agent(LMA)program running on MPS.By this method,the Operating System(OS)kernel,key software and data of the MPS can be dynamically measured without disturbance,which makes it difficult for adversaries to attack through software.Besides,this architecture has been fully verified on FPGA prototype system.Compared with the existing systems,our architecture achieves higher security and is more efficient on DIM,which can fully supervise the running of application and aircraft hardware OS.

Towards functional verifying a family of SystemC TLMs

It is often the case that in the development of a system-on-a-chip(SoC)design,a family of SystemC transaction level models(TLM)is created.TLMs in the same family often share common functionalities but differ in their timing,implementation,configuration and performance in various SoC developing phases.In most cases,all the TLMs in a family must be verified for the follow-up design activities.In our previous work,we proposed to call such family TLM product line(TPL),and proposed feature-oriented(FO)design methodology for efficient TPL development.However,developers can only verify TLM in a family one by one,which causes large portion of duplicated verification overhead.Therefore,in our proposed methodology,functional verification of TPL has become a bottleneck.In this paper,we proposed a novel TPL verification method for FO designs.In our method,for the given property,we can exponentially reduce the number of TLMs to be verified by identifying mutefeature-modules(MFM),which will avoid duplicated veri-fication.The proposed method is presented in informal and formal way,and the correctness of it is proved.The theoretical analysis and experimental results on a real design show the correctness and efficiency of the proposed method.

A micro amperometric immunosensor for detection of human immunoglobulin

A novel amperometric immunosensor based on the micro electromechanical systems （MEMS） technology, using protein A and self-assembled monolayers （SAMs） for the orientation-controlled immobilization of antibodies, has been developed. Using MEMS technology, an ＂Au, Pt, Pt＂ three-microelectrode system enclosed in a SU-8 micro pool was fabricated. Employing SAMs, a monolayer of protein A was immobilized on the cysteamine modified Au electrode to achieve the orientation-controlled immobilization of the human immunoglobulin （HIgG） antibody. The immunosensor aimed at low unit cost, small dimension, high level of integration and the prospect of a biosensor system-on-a-chip. Cyclic voltammetry and chronoamperometry were conducted to characterize the immunosensor. Compared with the traditional immunosensor using bulky gold electrode or screen-printed electrode and the procedure directly binding protein A to electrode for immobilization of antibodies, it had attractive advantages, such as miniaturization, compatibility with CMOS technology, fast response （30 s）, broad linear range （50-400 pg/L） and low detection limit （10 pg/L） for HIgG. In addition, this immunosensor was easy to be designed into micro array and to realize the simultaneously multi-parameter detection.