ADVANCED FREQUENCY-DIRECTED RUN-LENTH BASED CODING SCHEME ON TEST DATA COMPRESSION FOR SYSTEM-ON-CHIP

Test data compression and test resource partitioning （TRP） are essential to reduce the amount of test data in system-on-chip testing. A novel variable-to-variable-length compression codes is designed as advanced fre- quency-directed run-length （AFDR） codes. Different [rom frequency-directed run-length （FDR） codes, AFDR encodes both 0- and 1-runs and uses the same codes to the equal length runs. It also modifies the codes for 00 and 11 to improve the compression performance. Experimental results for ISCAS 89 benchmark circuits show that AFDR codes achieve higher compression ratio than FDR and other compression codes.

Single-event effects induced by medium-energy protons in 28 nm system-on-chip

Single-event effects(SEEs)induced by mediumenergy protons in a 28 nm system-on-chip(SoC)were investigated at the China Institute of Atomic Energy.An on-chip memory block was irradiated with 90 MeV and 70 MeV protons,respectively.Single-bit upset and multicell upset events were observed,and an uppermost number of nine upset cells were discovered in the 90 MeV proton irradiation test.The results indicate that the SEE sensitivities of the 28 nm SoC to the 90 MeV and 70 MeV protons were similar.Cosmic Ray Effects on Micro-Electronics Monte Carlo simulations were analyzed,and it demonstrates that protons can induce effects in a 28 nm SoC if their energies are greater than 1.4 MeV and that the lowest corresponding linear energy transfer was 0.142 MeV cm^2 mg^-1.The similarities and discrepancies of the SEEs induced by the 90 MeV and 70 MeV protons were analyzed.

Random testing for system-level functional verification of system-on-chip

In order to deal with the limitations during the register transfer level verification, a new functional verification method based on the random testing for the system-level of system-on-chip is proposed.The validity of this method is proven theoretically.Specifically, testcases are generated according to many approaches of randomization.Moreover, the testbench for the system-level verification according to the proposed method is designed by using advanced modeling language.Therefore, under the circumstances that the testbench generates testcases quickly, the hardware/software co-simulation and co-verification can be implemented and the hardware/software partitioning planning can be evaluated easily.The comparison method is put to use in the evaluation approach of the testing validity.The evaluation result indicates that the efficiency of the partition testing is better than that of the random testing only when one or more subdomains are covered over with the area of errors, although the efficiency of the random testing is generally better than that of the partition testing.The experimental result indicates that this method has a good performance in the functional coverage and the cost of testing and can discover the functional errors as soon as possible.

Investigation of single event effect in 28-nm system-on-chip with multi patterns

Single event effects (SEEs) in a 28-nm system-on-chip (SoC) were assessed using heavy ion irradiations, and susceptibilities in different processor configurations with data accessing patterns were investigated. The patterns included the sole processor (SP) and asymmetric multiprocessing (AMP) patterns with static and dynamic data accessing. Single event upset (SEU) cross sections in static accessing can be more than twice as high as those of the dynamic accessing, and processor configuration pattern is not a critical factor for the SEU cross sections. Cross section interval of upset events was evaluated and the soft error rates in aerospace environment were predicted for the SoC. The tests also indicated that ultra-high linear energy transfer (LET) particle can cause exception currents in the 28-nm SoC, and some even are lower than the normal case.

A 130-nm ferroelectric nonvolatile system-on-chip for internet of things

IEEE J.Solid-State Circuits,2019,doi:10.1109/JSSC.2018.2884349Nonvolatile processor(NVP)is promising for energy-harvesting-powered internet-of-things(IoT)devices,owing to its unique capability to sustain computation progress over power outages.Recently.

Scheduling method based on virtual flattened architecture for Hierarchical system-on-chip

As the technology of IP-core-reused has been widely used, a lot of intellectual property （IP） cores have been embedded in different layers of system-on-chip （SOC）. Although the cycles of development and overhead are reduced by this method, it is a challenge to the SOC test. This paper proposes a scheduling method based on the virtual flattened architecture for hierarchical SOC, which breaks the hierarchical architecture to the virtual flattened one. Moreover, this method has more advantages compared with the traditional one, which tests the parent cores and child cores separately. Finally, the method is verified by the ITC＇02 benchmark, and gives good results that reduce the test time and overhead effectively.

Reconfigurable Ultrasonic Testing System Development Using Programmable Analog Front-End and Reconfigurable System-on-Chip Hardware

Ultrasonic testing systems have been extensively used in medical imaging and non-destructive testing applications. Generally, these systems aim at a particular application or target material. To make these systems portable and more adaptable to the test environments, this study presents a reconfigurable ultrasonic testing system (RUTS), which possesses dynamic reconfiguration capabilities. RUTS consists a fully programmable Analog Front-End (AFE), which facilitates beamforming and signal conditioning for variety of applications. RUTS AFE supports up to 8 transducers for phased-array implementation. Xilinx Zynq System-on-Chip (SoC) based Zedboard provides the back-end processing of RUTS. The powerful ARM embedded processor available within Zynq SoC manages the ultrasonic data acquisition/processing and overall system control, which makes RUTS a unique platform for the ultrasonic researchers to experiment and evaluate a wide range of real-time ultrasonic signal processing applications. This Linux-based system is utilized for ultra-sonic data compression implementation providing a versatile environment for further development of ultrasonic imaging and testing system. Furthermore, this study demonstrates the capabilities of RUTS by performing ultrasonic data acquisition and data compression in real-time. Thus, this reconfigurable system enables ultrasonic designers and researchers to efficiently prototype different experiments and to incorporate and analyze high performance ultrasonic signal and image processing algorithms.

三种SoC片上总线的分析与比较

随着以IP核复用为基础的SoC设计技术的发展,工业界及研究组织正积极从事相关IP互联标准方案的制定工作。本文介绍了目前SoC设计中常用的三种片上总线标准,即IBM公司的CoreConnect总线、ARM公司的AMBA总线和OCPIP组织的OCP总线,重点分析和比较了它们的特性,并针对它们不同的特点,阐述其合适的应用领域。

生化微传感SOC片内嵌入ADC的设计与实现

首先根据生化微传感SOC的应用场合和微传感器的特点,选定CR SAR ADC作为片内嵌入类型;基于SOC的标准CMOS工艺实现和低功耗的设计目标,分别进行了电容阵列、比较器、开关阵列和SAR控制逻辑等组成单元全定制原理图、版图设计,实现了片内嵌入10位ADC的整体芯片.流片实测结果DNL、INL最大值分别为+/-1.0LSB、+/-1.5LSB,功耗仅为4.62mW,满足生化微传感SOC数据转换的片内嵌入要求.

基于SOC与触摸屏技术的硬笔书法练习设备的设计

在电子产品设计过程中要充分考虑系统自身特点,根据需要设计并解决各个功能模块。本课题依据系统在设计和使用中涉及的各种状态及数据,结合现代电子技术与数据处理技术,提出适合于该硬笔书法练习系统的解决方案,并基于硬件系统实现各模块的功能,证明了方案的正确性及可实现性。

基于SoC芯片的嵌入式医学检测设备平台设计

本文将嵌入式系统应用于医学检测设备的开发中,设计了以SoC芯片为核心的嵌入式医学检测设备平台,介绍并探讨了其软硬件系统的基本原理、设计思想、实现方法,并在最后介绍了一个实用的例子。通过医学检测设备软硬件平台,可有效避免设备开发时的重复工作,减少系统的研发时间和成本,缩短推出新产品的时间。

Co-design for an SoC embedded network controller

With the development of Ethernet systems and the growing capacity of modem silicon technology, embedded communication networks are playing an increasingly important role in embedded and safety critical systems. Hardware/software co-design is a methodology for solving design problems in processor based embedded systems. In this work, we implemented a new 1-cycle pipeline microprocessor and a fast Ethemet transceiver and established a low cost, high performance embedded network controller, and designed a TCP/IP stack to access the Intemet. We discussed the hardware/software architecture in the forepart, and then the whole system-on-a-chip on Altera Stratix EP1S25F780C6 device. Using the FPGA environment and SmartBit tester, we tested the system＇s throughput. Our simulation results showed that the maximum throughput of Ethemet packets is up to 7 Mbps, that of UDP packets is up to 5.8 Mbps, and that of TCP packets is up to 3.4 Mbps, which showed that this embedded system can easily transmit basic voice and video signals through Ethemet, and that using only one chip can realize that many electronic devices access to the Intemet directly and get high performance.

A front-end automation tool supporting design, verification and reuse of SOC

This paper describes an in-house developed language tool called VPerl used in developing a 250 MHz 32-bit high-performance low power embedded CPU core. The authors showed that use of this tool can compress the Verilog code by more than a factor of 5, increase the efficiency of the front-end design, reduce the bug rate significantly. This tool can be used to enhance the reusability of an intellectual property model, and facilitate porting design for different platforms.

Stepping Control Method of Linear Displacement Mechanism Driven by TRUM Based on PSoC

A method based on programmable system-on-chip(PSoC)is proposed to realize high resolution stepping motion control of liner displacement mechanism driven by traveling wave rotary ultrasonic motors(TRUM).Intelligent controller of stepping ultrasonic motor consists of PSoC microprocessor.Continuous square wave signal is sent out by the pulse width modulator(PWM)module inside PSoC,and converted into sinusoidal signal which is essential to the motor′s normal working by power amplifier circuit.Subsequently,signal impulse transmission is realized by the counter control break,and the stepping motion of linear displacement mechanism based on TRUM is achieved.Running status of the ultrasonic motor is controlled by an upper computer.Control command is sent to PSoC through serial communication circuit of RS-232.Relative program and control interface are written in LabView.Finally the mechanism is tested by XL-80 laser interferometer.Test results show that the mechanism can provide a stable motion and a fixed step pitch with the displacement resolution of 6nm.

Macroblock-level decoding and deblocking method and its pipeline implementation in H.264 decoder SOC design

This paper presents a macroblock-level (MB-level) decoding and deblocking method for supporting the flexible macroblock ordering (FMO) and arbitrary slice ordering (ASO) bit streams in H.264 decoder and its SOC/ASIC implementation. By searching the slice containing the current macroblock in the bit stream and switching slices correctly, MBs can be decoded in the raster scan order, while the decoding process can immediately begin as long as the slice containing the current MB is available. This architectural modification enables the MB-level decoding and deblocking 3-stage pipeline, and saves about 20% of SDRAM bandwidth. Implementation results showed that the design achieves real-time decoding of 1080HD (1920×1088@30 fps) at a system clock of 166 MHz.

Signal processing for PSoC based PIR motion detection

A signal processing scheme for a programmable system-on-chip(PSoC)based human body infrared tracking system is described.The purpose of this project is to convert the analog signal from a passive infrared(PIR)sensor to a digital signal which will be used to calculate the correct position of a human body.This paper covers the analog design with PSoC,the analog to digital conversion and the software to eliminate noise.

单片集成计算机系统SOC(System—On—Chip)应用探讨

介绍了目前国际上新发展的单片集成计算机系统SOC(System—On—Chip),按照不同的用途,选取不同功能模块的芯片,只需要很少的外部器件就可以完成普通PC所具有的常用功能,功能比以往的微处理器要强大得多,它的内部属于PC的构架,可扩展性强,同时使产品具有体积小巧、成本低廉的优势。

Area-time associated test cost model for SoC and lower bound of test time

A novel test access mechanism （TAM） architecture with multi test-channel （TC） based on IEEE Standard 1500 is proposed instead of the traditional sub-TAM structure. The cost model of an area-time associated test and the corresponding lower bound of system-on-chip （SoC） test time are established based on this TAM architecture. The model provides a more reliable method to control the SoC scheduling and reduces the complexity in related algorithm research. The result based on the area time associated test cost model has been validated using the ITC02 test benchmark.

CORE-UNIFIED SOC TEST DATA COMPRESSION AND APPLICATION

The pattern run-length coding test data compression approach is extended by introducing don't care bit(x) propagation strategy into it.More than one core test sets for testing core-based System-on-Chip(SoC) are unified into a single one,which is compressed by the extended coding technique.A reconfigurable scan test application mechanism is presented,in which test data for multiple cores are scanned and captured jointly to make SoC test application more efficient with low hardware overhead added.The proposed union test technique is applied to an academic SoC embedded by six large ISCAS'89 benchmarks,and to an ITC' 02 benchmark circuit.Experiment results show that compared with the existing schemes in which a core test set is compressed and applied independently of other cores,the proposed scheme can not only improve test data compression/decompression,but also reduce the redundant shift and capture cycles during scan testing,decreasing SoC test application time effectively.

Domain Coverage Metric for SoC Validation

The importance of system-on-chip （SoC） validation continues to grow with the increase of design size. An innovative domain coverage metric is proposed to measure the completeness and quality of validation approach. Domain methodology is based on a geometrical analysis of the domain boundary and takes advantage of the fact that the point on or near the boundary is the most sensitive to domain errors. The coverage tool has been implemented using Verilog procedural interface （VPI） and applied to validation of SoC under design. Results show that the domain coverage can detect many design faults which statement and path coverage can not.