Single-event effects(SEEs)induced by mediumenergy protons in a 28 nm system-on-chip(SoC)were investigated at the China Institute of Atomic Energy.An on-chip memory block was irradiated with 90 MeV and 70 MeV protons,r...Single-event effects(SEEs)induced by mediumenergy protons in a 28 nm system-on-chip(SoC)were investigated at the China Institute of Atomic Energy.An on-chip memory block was irradiated with 90 MeV and 70 MeV protons,respectively.Single-bit upset and multicell upset events were observed,and an uppermost number of nine upset cells were discovered in the 90 MeV proton irradiation test.The results indicate that the SEE sensitivities of the 28 nm SoC to the 90 MeV and 70 MeV protons were similar.Cosmic Ray Effects on Micro-Electronics Monte Carlo simulations were analyzed,and it demonstrates that protons can induce effects in a 28 nm SoC if their energies are greater than 1.4 MeV and that the lowest corresponding linear energy transfer was 0.142 MeV cm^2 mg^-1.The similarities and discrepancies of the SEEs induced by the 90 MeV and 70 MeV protons were analyzed.展开更多
In order to deal with the limitations during the register transfer level verification, a new functional verification method based on the random testing for the system-level of system-on-chip is proposed.The validity o...In order to deal with the limitations during the register transfer level verification, a new functional verification method based on the random testing for the system-level of system-on-chip is proposed.The validity of this method is proven theoretically.Specifically, testcases are generated according to many approaches of randomization.Moreover, the testbench for the system-level verification according to the proposed method is designed by using advanced modeling language.Therefore, under the circumstances that the testbench generates testcases quickly, the hardware/software co-simulation and co-verification can be implemented and the hardware/software partitioning planning can be evaluated easily.The comparison method is put to use in the evaluation approach of the testing validity.The evaluation result indicates that the efficiency of the partition testing is better than that of the random testing only when one or more subdomains are covered over with the area of errors, although the efficiency of the random testing is generally better than that of the partition testing.The experimental result indicates that this method has a good performance in the functional coverage and the cost of testing and can discover the functional errors as soon as possible.展开更多
Single event effects (SEEs) in a 28-nm system-on-chip (SoC) were assessed using heavy ion irradiations, and susceptibilities in different processor configurations with data accessing patterns were investigated. The pa...Single event effects (SEEs) in a 28-nm system-on-chip (SoC) were assessed using heavy ion irradiations, and susceptibilities in different processor configurations with data accessing patterns were investigated. The patterns included the sole processor (SP) and asymmetric multiprocessing (AMP) patterns with static and dynamic data accessing. Single event upset (SEU) cross sections in static accessing can be more than twice as high as those of the dynamic accessing, and processor configuration pattern is not a critical factor for the SEU cross sections. Cross section interval of upset events was evaluated and the soft error rates in aerospace environment were predicted for the SoC. The tests also indicated that ultra-high linear energy transfer (LET) particle can cause exception currents in the 28-nm SoC, and some even are lower than the normal case.展开更多
IEEE J.Solid-State Circuits,2019,doi:10.1109/JSSC.2018.2884349Nonvolatile processor(NVP)is promising for energy-harvesting-powered internet-of-things(IoT)devices,owing to its unique capability to sustain computation p...IEEE J.Solid-State Circuits,2019,doi:10.1109/JSSC.2018.2884349Nonvolatile processor(NVP)is promising for energy-harvesting-powered internet-of-things(IoT)devices,owing to its unique capability to sustain computation progress over power outages.Recently.展开更多
As the technology of IP-core-reused has been widely used, a lot of intellectual property (IP) cores have been embedded in different layers of system-on-chip (SOC). Although the cycles of development and overhead a...As the technology of IP-core-reused has been widely used, a lot of intellectual property (IP) cores have been embedded in different layers of system-on-chip (SOC). Although the cycles of development and overhead are reduced by this method, it is a challenge to the SOC test. This paper proposes a scheduling method based on the virtual flattened architecture for hierarchical SOC, which breaks the hierarchical architecture to the virtual flattened one. Moreover, this method has more advantages compared with the traditional one, which tests the parent cores and child cores separately. Finally, the method is verified by the ITC'02 benchmark, and gives good results that reduce the test time and overhead effectively.展开更多
Ultrasonic testing systems have been extensively used in medical imaging and non-destructive testing applications. Generally, these systems aim at a particular application or target material. To make these systems por...Ultrasonic testing systems have been extensively used in medical imaging and non-destructive testing applications. Generally, these systems aim at a particular application or target material. To make these systems portable and more adaptable to the test environments, this study presents a reconfigurable ultrasonic testing system (RUTS), which possesses dynamic reconfiguration capabilities. RUTS consists a fully programmable Analog Front-End (AFE), which facilitates beamforming and signal conditioning for variety of applications. RUTS AFE supports up to 8 transducers for phased-array implementation. Xilinx Zynq System-on-Chip (SoC) based Zedboard provides the back-end processing of RUTS. The powerful ARM embedded processor available within Zynq SoC manages the ultrasonic data acquisition/processing and overall system control, which makes RUTS a unique platform for the ultrasonic researchers to experiment and evaluate a wide range of real-time ultrasonic signal processing applications. This Linux-based system is utilized for ultra-sonic data compression implementation providing a versatile environment for further development of ultrasonic imaging and testing system. Furthermore, this study demonstrates the capabilities of RUTS by performing ultrasonic data acquisition and data compression in real-time. Thus, this reconfigurable system enables ultrasonic designers and researchers to efficiently prototype different experiments and to incorporate and analyze high performance ultrasonic signal and image processing algorithms.展开更多
首先根据生化微传感SOC的应用场合和微传感器的特点,选定CR SAR ADC作为片内嵌入类型;基于SOC的标准CMOS工艺实现和低功耗的设计目标,分别进行了电容阵列、比较器、开关阵列和SAR控制逻辑等组成单元全定制原理图、版图设计,实现了片内嵌...首先根据生化微传感SOC的应用场合和微传感器的特点,选定CR SAR ADC作为片内嵌入类型;基于SOC的标准CMOS工艺实现和低功耗的设计目标,分别进行了电容阵列、比较器、开关阵列和SAR控制逻辑等组成单元全定制原理图、版图设计,实现了片内嵌入10位ADC的整体芯片.流片实测结果DNL、INL最大值分别为+/-1.0LSB、+/-1.5LSB,功耗仅为4.62mW,满足生化微传感SOC数据转换的片内嵌入要求.展开更多
First-Input-First-Output (FIFO) buffers are extensively used in contemporary digital processors and System-on-Chips (SoC). There are synchronous FIFOs and asycnrhonous FIFOs. And different sized FIFOs should be implem...First-Input-First-Output (FIFO) buffers are extensively used in contemporary digital processors and System-on-Chips (SoC). There are synchronous FIFOs and asycnrhonous FIFOs. And different sized FIFOs should be implemented in different ways. FIFOs are used not only for the pipeline design within a processor, for the inter-processor communication networks, for example Network-on-Chips (NoCs), but also for the peripherals and the clock domain crossing at the whole SoC level. In this paper, we review the interface, the circuit implementation, and the various usages of FIFOs in various levels of the digital design. We can find that the usage of FIFOs could greatly facilitate the signal storage, signal decoupling, signal transfer, power domain separation and power domain crossing in digital systems. We hope that more attentions are paid to the usages of synchronous and asynchronous FIFOs and more sophististicated usages are discovered by the digital design communities.展开更多
A method based on programmable system-on-chip(PSoC)is proposed to realize high resolution stepping motion control of liner displacement mechanism driven by traveling wave rotary ultrasonic motors(TRUM).Intelligent con...A method based on programmable system-on-chip(PSoC)is proposed to realize high resolution stepping motion control of liner displacement mechanism driven by traveling wave rotary ultrasonic motors(TRUM).Intelligent controller of stepping ultrasonic motor consists of PSoC microprocessor.Continuous square wave signal is sent out by the pulse width modulator(PWM)module inside PSoC,and converted into sinusoidal signal which is essential to the motor′s normal working by power amplifier circuit.Subsequently,signal impulse transmission is realized by the counter control break,and the stepping motion of linear displacement mechanism based on TRUM is achieved.Running status of the ultrasonic motor is controlled by an upper computer.Control command is sent to PSoC through serial communication circuit of RS-232.Relative program and control interface are written in LabView.Finally the mechanism is tested by XL-80 laser interferometer.Test results show that the mechanism can provide a stable motion and a fixed step pitch with the displacement resolution of 6nm.展开更多
A signal processing scheme for a programmable system-on-chip(PSoC)based human body infrared tracking system is described.The purpose of this project is to convert the analog signal from a passive infrared(PIR)sensor t...A signal processing scheme for a programmable system-on-chip(PSoC)based human body infrared tracking system is described.The purpose of this project is to convert the analog signal from a passive infrared(PIR)sensor to a digital signal which will be used to calculate the correct position of a human body.This paper covers the analog design with PSoC,the analog to digital conversion and the software to eliminate noise.展开更多
A novel test access mechanism (TAM) architecture with multi test-channel (TC) based on IEEE Standard 1500 is proposed instead of the traditional sub-TAM structure. The cost model of an area-time associated test an...A novel test access mechanism (TAM) architecture with multi test-channel (TC) based on IEEE Standard 1500 is proposed instead of the traditional sub-TAM structure. The cost model of an area-time associated test and the corresponding lower bound of system-on-chip (SoC) test time are established based on this TAM architecture. The model provides a more reliable method to control the SoC scheduling and reduces the complexity in related algorithm research. The result based on the area time associated test cost model has been validated using the ITC02 test benchmark.展开更多
The pattern run-length coding test data compression approach is extended by introducing don't care bit(x) propagation strategy into it.More than one core test sets for testing core-based System-on-Chip(SoC) are un...The pattern run-length coding test data compression approach is extended by introducing don't care bit(x) propagation strategy into it.More than one core test sets for testing core-based System-on-Chip(SoC) are unified into a single one,which is compressed by the extended coding technique.A reconfigurable scan test application mechanism is presented,in which test data for multiple cores are scanned and captured jointly to make SoC test application more efficient with low hardware overhead added.The proposed union test technique is applied to an academic SoC embedded by six large ISCAS'89 benchmarks,and to an ITC' 02 benchmark circuit.Experiment results show that compared with the existing schemes in which a core test set is compressed and applied independently of other cores,the proposed scheme can not only improve test data compression/decompression,but also reduce the redundant shift and capture cycles during scan testing,decreasing SoC test application time effectively.展开更多
The importance of system-on-chip (SoC) validation continues to grow with the increase of design size. An innovative domain coverage metric is proposed to measure the completeness and quality of validation approach. ...The importance of system-on-chip (SoC) validation continues to grow with the increase of design size. An innovative domain coverage metric is proposed to measure the completeness and quality of validation approach. Domain methodology is based on a geometrical analysis of the domain boundary and takes advantage of the fact that the point on or near the boundary is the most sensitive to domain errors. The coverage tool has been implemented using Verilog procedural interface (VPI) and applied to validation of SoC under design. Results show that the domain coverage can detect many design faults which statement and path coverage can not.展开更多
With the prevalence of big-data technology,intricate,nanoscale Multi-Processor System-on-Chips(MP-SoCs)have been used in various safety-critical applications.However,with no extra countermeasures taken,this widespread...With the prevalence of big-data technology,intricate,nanoscale Multi-Processor System-on-Chips(MP-SoCs)have been used in various safety-critical applications.However,with no extra countermeasures taken,this widespread use of MP-SoCs can lead to an undesirable decrease in their dependability.This study presents a promising approach using a group of Embedded Instruments(EIs)inside a processor core for health monitoring.Multiple health monitoring datasets obtained from the employed EIs are sampled and collated via the implemented experiment and thereafter used for conducting its remaining useful lifetime prognostics.This enables MP-SoCs to undertake preventive self-repair,thus realizing a zero mean downtime system and ensuring improved dependability.In addition,a principal component analysis based algorithm is designed for realizing the EI data fusion.Subsequently,a genetic algorithm based degradation optimization is employed to create a lifetime prediction model with respect to the processor.展开更多
Power Station(PS)monitoring systems are becoming critical,ensuring electrical safety through early warning,and in the event of a PS fault,the power supply is quickly disconnected.Traditional technologies are based on ...Power Station(PS)monitoring systems are becoming critical,ensuring electrical safety through early warning,and in the event of a PS fault,the power supply is quickly disconnected.Traditional technologies are based on relays and don’t have a way to capture and store user data when there is a problem.The proposed framework is designed with the goal of providing smart environments for protecting electrical types of equipment.This paper proposes an Internet of Things(IoT)-based Smart Framework(SF)for monitoring the Power Devices(PD)which are being used in power substations.A Real-Time Monitoring(RTM)system is proposed,and it uses a state-of-the-art smart IoT-based System on Chip(SoC)sensors,a Hybrid Prediction Model(HPM),and it is being used in Big Data Processing(BDP).The Cloud Server(CS)processes the data and does the data analytics by comparing it with the historical data already stored in the CS.No-Structural Query Language Mongo Data Base(MDB)is used to store Sensor Data(SD)from the PSs.The proposed HPM combines the Density-Based Spatial Clustering of Applications with Noise(DBSCAN)-algorithm for Outlier Detection(OD)and the Random Forest(RF)classification algorithm for removing the outlier SD and providing Fault Detection(FD)when the PD isn’t working.The suggested work is assessed and tested under various fault circumstances that happened in PSs.The simulation outcome proves that the proposed model is effective in monitoring the smooth functioning of the PS.Also,the suggested HPM has a higher Fault Prediction(FP)accuracy.This means that faults can be found earlier,early warning signals can be sent,and the power supply can be turned off quickly to ensure electrical safety.A powerful RTM and event warning system can also be built into the system before faults happen.展开更多
As deep learning techniques such as Convolutional Neural Networks(CNNs)are widely adopted,the complexity of CNNs is rapidly increasing due to the growing demand for CNN accelerator system-on-chip(SoC).Although convent...As deep learning techniques such as Convolutional Neural Networks(CNNs)are widely adopted,the complexity of CNNs is rapidly increasing due to the growing demand for CNN accelerator system-on-chip(SoC).Although conventional CNN accelerators can reduce the computational time of learning and inference tasks,they tend to occupy large chip areas due to many multiply-and-accumulate(MAC)operators when implemented in complex digital circuits,incurring excessive power consumption.To overcome these drawbacks,this work implements an analog convolutional filter consisting of an analog multiply-and-accumulate arithmetic circuit along with an analog-to-digital converter(ADC).This paper introduces the architecture of an analog convolutional kernel comprised of low-power ultra-small circuits for neural network accelerator chips.ADC is an essential component of the analog convolutional kernel used to convert the analog convolutional result to digital values to be stored in memory.This work presents the implementation of a highly low-power and area-efficient 12-bit Successive Approximation Register(SAR)ADC.Unlink most other SAR-ADCs with differential structure;the proposed ADC employs a single-ended capacitor array to support the preceding single-ended max-pooling circuit along with minimal power consumption.The SARADCimplementation also introduces a unique circuit that reduces kick-back noise to increase performance.It was implemented in a test chip using a 55 nm CMOS process.It demonstrates that the proposed ADC reduces Kick-back noise by 40%and consequently improves the ADC’s resolution by about 10%while providing a near rail-to-rail dynamic rangewith significantly lower power consumption than conventional ADCs.The ADC test chip shows a chip size of 4600μm^(2)with a power consumption of 6.6μW while providing an signal-to-noise-and-distortion ratio(SNDR)of 68.45 dB,corresponding to an effective number of bits(ENOB)of 11.07 bits.展开更多
基金supported by the National Natural Science Foundation of China(Grant Nos.11575138,11835006,11690040,and 11690043)
文摘Single-event effects(SEEs)induced by mediumenergy protons in a 28 nm system-on-chip(SoC)were investigated at the China Institute of Atomic Energy.An on-chip memory block was irradiated with 90 MeV and 70 MeV protons,respectively.Single-bit upset and multicell upset events were observed,and an uppermost number of nine upset cells were discovered in the 90 MeV proton irradiation test.The results indicate that the SEE sensitivities of the 28 nm SoC to the 90 MeV and 70 MeV protons were similar.Cosmic Ray Effects on Micro-Electronics Monte Carlo simulations were analyzed,and it demonstrates that protons can induce effects in a 28 nm SoC if their energies are greater than 1.4 MeV and that the lowest corresponding linear energy transfer was 0.142 MeV cm^2 mg^-1.The similarities and discrepancies of the SEEs induced by the 90 MeV and 70 MeV protons were analyzed.
基金supported by the National High Technology Research and Development Program of China (863 Program) (2002AA1Z1490)Specialized Research Fund for the Doctoral Program of Higher Education (20040486049)the University Cooperative Research Fund of Huawei Technology Co., Ltd
文摘In order to deal with the limitations during the register transfer level verification, a new functional verification method based on the random testing for the system-level of system-on-chip is proposed.The validity of this method is proven theoretically.Specifically, testcases are generated according to many approaches of randomization.Moreover, the testbench for the system-level verification according to the proposed method is designed by using advanced modeling language.Therefore, under the circumstances that the testbench generates testcases quickly, the hardware/software co-simulation and co-verification can be implemented and the hardware/software partitioning planning can be evaluated easily.The comparison method is put to use in the evaluation approach of the testing validity.The evaluation result indicates that the efficiency of the partition testing is better than that of the random testing only when one or more subdomains are covered over with the area of errors, although the efficiency of the random testing is generally better than that of the partition testing.The experimental result indicates that this method has a good performance in the functional coverage and the cost of testing and can discover the functional errors as soon as possible.
基金Project supported by the National Natural Science Foundation of China(Grant Nos.11575138,11835006,11690040,and 11690043)the Fund from Innovation Center of Radiation Application(Grant No.KFZC2019050321)+1 种基金the Fund from the Science and Technology on Vacuum Technology and Physics Laboratory,Lanzhou Institute of Physics(Grant No.ZWK1804)the Program of China Scholarships Council(Grant No.201906280343)。
文摘Single event effects (SEEs) in a 28-nm system-on-chip (SoC) were assessed using heavy ion irradiations, and susceptibilities in different processor configurations with data accessing patterns were investigated. The patterns included the sole processor (SP) and asymmetric multiprocessing (AMP) patterns with static and dynamic data accessing. Single event upset (SEU) cross sections in static accessing can be more than twice as high as those of the dynamic accessing, and processor configuration pattern is not a critical factor for the SEU cross sections. Cross section interval of upset events was evaluated and the soft error rates in aerospace environment were predicted for the SoC. The tests also indicated that ultra-high linear energy transfer (LET) particle can cause exception currents in the 28-nm SoC, and some even are lower than the normal case.
文摘IEEE J.Solid-State Circuits,2019,doi:10.1109/JSSC.2018.2884349Nonvolatile processor(NVP)is promising for energy-harvesting-powered internet-of-things(IoT)devices,owing to its unique capability to sustain computation progress over power outages.Recently.
基金Project supported by the Applied Materials Foundation Project of Science and Technology Commission of Shanghai Mu-nicipality (Grant No.08700741000)the System Design on Chip Project of Science and Technology Commission of Shanghai Municipality (Grant No.08706201000)+1 种基金the Leading Academic Discipline Project of Shanghai Municipal Education Committee(Grant No.J50104)the Innovation Foundation Project of Shanghai University
文摘As the technology of IP-core-reused has been widely used, a lot of intellectual property (IP) cores have been embedded in different layers of system-on-chip (SOC). Although the cycles of development and overhead are reduced by this method, it is a challenge to the SOC test. This paper proposes a scheduling method based on the virtual flattened architecture for hierarchical SOC, which breaks the hierarchical architecture to the virtual flattened one. Moreover, this method has more advantages compared with the traditional one, which tests the parent cores and child cores separately. Finally, the method is verified by the ITC'02 benchmark, and gives good results that reduce the test time and overhead effectively.
文摘Ultrasonic testing systems have been extensively used in medical imaging and non-destructive testing applications. Generally, these systems aim at a particular application or target material. To make these systems portable and more adaptable to the test environments, this study presents a reconfigurable ultrasonic testing system (RUTS), which possesses dynamic reconfiguration capabilities. RUTS consists a fully programmable Analog Front-End (AFE), which facilitates beamforming and signal conditioning for variety of applications. RUTS AFE supports up to 8 transducers for phased-array implementation. Xilinx Zynq System-on-Chip (SoC) based Zedboard provides the back-end processing of RUTS. The powerful ARM embedded processor available within Zynq SoC manages the ultrasonic data acquisition/processing and overall system control, which makes RUTS a unique platform for the ultrasonic researchers to experiment and evaluate a wide range of real-time ultrasonic signal processing applications. This Linux-based system is utilized for ultra-sonic data compression implementation providing a versatile environment for further development of ultrasonic imaging and testing system. Furthermore, this study demonstrates the capabilities of RUTS by performing ultrasonic data acquisition and data compression in real-time. Thus, this reconfigurable system enables ultrasonic designers and researchers to efficiently prototype different experiments and to incorporate and analyze high performance ultrasonic signal and image processing algorithms.
文摘首先根据生化微传感SOC的应用场合和微传感器的特点,选定CR SAR ADC作为片内嵌入类型;基于SOC的标准CMOS工艺实现和低功耗的设计目标,分别进行了电容阵列、比较器、开关阵列和SAR控制逻辑等组成单元全定制原理图、版图设计,实现了片内嵌入10位ADC的整体芯片.流片实测结果DNL、INL最大值分别为+/-1.0LSB、+/-1.5LSB,功耗仅为4.62mW,满足生化微传感SOC数据转换的片内嵌入要求.
文摘First-Input-First-Output (FIFO) buffers are extensively used in contemporary digital processors and System-on-Chips (SoC). There are synchronous FIFOs and asycnrhonous FIFOs. And different sized FIFOs should be implemented in different ways. FIFOs are used not only for the pipeline design within a processor, for the inter-processor communication networks, for example Network-on-Chips (NoCs), but also for the peripherals and the clock domain crossing at the whole SoC level. In this paper, we review the interface, the circuit implementation, and the various usages of FIFOs in various levels of the digital design. We can find that the usage of FIFOs could greatly facilitate the signal storage, signal decoupling, signal transfer, power domain separation and power domain crossing in digital systems. We hope that more attentions are paid to the usages of synchronous and asynchronous FIFOs and more sophististicated usages are discovered by the digital design communities.
基金supported by the National Natural Science Foundation of China(Nos.50905085,91116020)the National Science Foundation for Post-Doctoral Scientists of China(No.2012M511263)the Aviation Science Foundation of China(No.20100112005)
文摘A method based on programmable system-on-chip(PSoC)is proposed to realize high resolution stepping motion control of liner displacement mechanism driven by traveling wave rotary ultrasonic motors(TRUM).Intelligent controller of stepping ultrasonic motor consists of PSoC microprocessor.Continuous square wave signal is sent out by the pulse width modulator(PWM)module inside PSoC,and converted into sinusoidal signal which is essential to the motor′s normal working by power amplifier circuit.Subsequently,signal impulse transmission is realized by the counter control break,and the stepping motion of linear displacement mechanism based on TRUM is achieved.Running status of the ultrasonic motor is controlled by an upper computer.Control command is sent to PSoC through serial communication circuit of RS-232.Relative program and control interface are written in LabView.Finally the mechanism is tested by XL-80 laser interferometer.Test results show that the mechanism can provide a stable motion and a fixed step pitch with the displacement resolution of 6nm.
文摘A signal processing scheme for a programmable system-on-chip(PSoC)based human body infrared tracking system is described.The purpose of this project is to convert the analog signal from a passive infrared(PIR)sensor to a digital signal which will be used to calculate the correct position of a human body.This paper covers the analog design with PSoC,the analog to digital conversion and the software to eliminate noise.
基金Project supported by the SDC Project of Science and Technology Commission of Shanghai Municipality (Grant No.08706201000)the AM Foundation Project of Science and Technology Commission of Shanghai Municipality (Grant No.08700741000)+1 种基金the Leading Academic Discipline Project of Shanghai Education Commission (Grant No.J50104)the Innovation Foundation Project of Shanghai University
文摘A novel test access mechanism (TAM) architecture with multi test-channel (TC) based on IEEE Standard 1500 is proposed instead of the traditional sub-TAM structure. The cost model of an area-time associated test and the corresponding lower bound of system-on-chip (SoC) test time are established based on this TAM architecture. The model provides a more reliable method to control the SoC scheduling and reduces the complexity in related algorithm research. The result based on the area time associated test cost model has been validated using the ITC02 test benchmark.
基金Supported by the National Natural Science Fund of China (No.60876028)the key Project of Natural Science Foundation of the Anhui Higher Education Institutions (No.KJ2010A280)
文摘The pattern run-length coding test data compression approach is extended by introducing don't care bit(x) propagation strategy into it.More than one core test sets for testing core-based System-on-Chip(SoC) are unified into a single one,which is compressed by the extended coding technique.A reconfigurable scan test application mechanism is presented,in which test data for multiple cores are scanned and captured jointly to make SoC test application more efficient with low hardware overhead added.The proposed union test technique is applied to an academic SoC embedded by six large ISCAS'89 benchmarks,and to an ITC' 02 benchmark circuit.Experiment results show that compared with the existing schemes in which a core test set is compressed and applied independently of other cores,the proposed scheme can not only improve test data compression/decompression,but also reduce the redundant shift and capture cycles during scan testing,decreasing SoC test application time effectively.
文摘The importance of system-on-chip (SoC) validation continues to grow with the increase of design size. An innovative domain coverage metric is proposed to measure the completeness and quality of validation approach. Domain methodology is based on a geometrical analysis of the domain boundary and takes advantage of the fact that the point on or near the boundary is the most sensitive to domain errors. The coverage tool has been implemented using Verilog procedural interface (VPI) and applied to validation of SoC under design. Results show that the domain coverage can detect many design faults which statement and path coverage can not.
基金This study was supported by the National Natural Science Foundation of China(Nos.12271259,12271098,and 11971349)EU project BASTION(No.619871)+2 种基金Horizon 2020 IMMORTAL(No.644905)Recore Systems B.V.(the Netherlands)Ridgetop Group Inc.(the Netherlands)are acknowledged for their contributions to IC design and measurement。
文摘With the prevalence of big-data technology,intricate,nanoscale Multi-Processor System-on-Chips(MP-SoCs)have been used in various safety-critical applications.However,with no extra countermeasures taken,this widespread use of MP-SoCs can lead to an undesirable decrease in their dependability.This study presents a promising approach using a group of Embedded Instruments(EIs)inside a processor core for health monitoring.Multiple health monitoring datasets obtained from the employed EIs are sampled and collated via the implemented experiment and thereafter used for conducting its remaining useful lifetime prognostics.This enables MP-SoCs to undertake preventive self-repair,thus realizing a zero mean downtime system and ensuring improved dependability.In addition,a principal component analysis based algorithm is designed for realizing the EI data fusion.Subsequently,a genetic algorithm based degradation optimization is employed to create a lifetime prediction model with respect to the processor.
基金The authors are grateful to the Taif University Researchers Supporting Project Number(TURSP-2020/36),Taif University,Taif,Saudi Arabia.
文摘Power Station(PS)monitoring systems are becoming critical,ensuring electrical safety through early warning,and in the event of a PS fault,the power supply is quickly disconnected.Traditional technologies are based on relays and don’t have a way to capture and store user data when there is a problem.The proposed framework is designed with the goal of providing smart environments for protecting electrical types of equipment.This paper proposes an Internet of Things(IoT)-based Smart Framework(SF)for monitoring the Power Devices(PD)which are being used in power substations.A Real-Time Monitoring(RTM)system is proposed,and it uses a state-of-the-art smart IoT-based System on Chip(SoC)sensors,a Hybrid Prediction Model(HPM),and it is being used in Big Data Processing(BDP).The Cloud Server(CS)processes the data and does the data analytics by comparing it with the historical data already stored in the CS.No-Structural Query Language Mongo Data Base(MDB)is used to store Sensor Data(SD)from the PSs.The proposed HPM combines the Density-Based Spatial Clustering of Applications with Noise(DBSCAN)-algorithm for Outlier Detection(OD)and the Random Forest(RF)classification algorithm for removing the outlier SD and providing Fault Detection(FD)when the PD isn’t working.The suggested work is assessed and tested under various fault circumstances that happened in PSs.The simulation outcome proves that the proposed model is effective in monitoring the smooth functioning of the PS.Also,the suggested HPM has a higher Fault Prediction(FP)accuracy.This means that faults can be found earlier,early warning signals can be sent,and the power supply can be turned off quickly to ensure electrical safety.A powerful RTM and event warning system can also be built into the system before faults happen.
基金This work was supported by the National Research Foundation of Korea(NRF)grant funded by theKorea government(MSIT)(No.2022R1A5A8026986)and supported by Institute of Information&communications Technology Planning&Evaluation(IITP)grant funded by the Korea government(MSIT)(No.2020-0-01304,Development of Self-learnable Mobile Recursive Neural Network Processor Technology)+3 种基金It was also supported by the MSIT(Ministry of Science and ICT),Korea,under the Grand Information Technology Research Center support program(IITP-2022-2020-0-01462)supervised by the“IITP(Institute for Information&communications Technology Planning&Evaluation)”supported by the National Research Foundation of Korea(NRF)grant funded by the Korea government(MSIT)(No.2021R1F1A1061314)In addition,this work was conducted during the research year of Chungbuk National University in 2020.
文摘As deep learning techniques such as Convolutional Neural Networks(CNNs)are widely adopted,the complexity of CNNs is rapidly increasing due to the growing demand for CNN accelerator system-on-chip(SoC).Although conventional CNN accelerators can reduce the computational time of learning and inference tasks,they tend to occupy large chip areas due to many multiply-and-accumulate(MAC)operators when implemented in complex digital circuits,incurring excessive power consumption.To overcome these drawbacks,this work implements an analog convolutional filter consisting of an analog multiply-and-accumulate arithmetic circuit along with an analog-to-digital converter(ADC).This paper introduces the architecture of an analog convolutional kernel comprised of low-power ultra-small circuits for neural network accelerator chips.ADC is an essential component of the analog convolutional kernel used to convert the analog convolutional result to digital values to be stored in memory.This work presents the implementation of a highly low-power and area-efficient 12-bit Successive Approximation Register(SAR)ADC.Unlink most other SAR-ADCs with differential structure;the proposed ADC employs a single-ended capacitor array to support the preceding single-ended max-pooling circuit along with minimal power consumption.The SARADCimplementation also introduces a unique circuit that reduces kick-back noise to increase performance.It was implemented in a test chip using a 55 nm CMOS process.It demonstrates that the proposed ADC reduces Kick-back noise by 40%and consequently improves the ADC’s resolution by about 10%while providing a near rail-to-rail dynamic rangewith significantly lower power consumption than conventional ADCs.The ADC test chip shows a chip size of 4600μm^(2)with a power consumption of 6.6μW while providing an signal-to-noise-and-distortion ratio(SNDR)of 68.45 dB,corresponding to an effective number of bits(ENOB)of 11.07 bits.