A three-terminal silicon-based light emitting device is proposed and fabricated in standard 0.35 μm complementary metal-oxide-semiconductor technology. This device is capable of versatile working modes: it can emit ...A three-terminal silicon-based light emitting device is proposed and fabricated in standard 0.35 μm complementary metal-oxide-semiconductor technology. This device is capable of versatile working modes: it can emit visible to near infra-red (NIR) light (the spectrum ranges from 500 nm to 1000 nm) in reverse bias avalanche breakdown mode with working voltage between 8.35 V-12 V and emit NIR light (the spectrum ranges from 900 nm to 1300 nm) in the forward injection mode with working voltage below 2 V. An apparent modulation effect on the light intensity from the polysilicon gate is observed in the forward injection mode. Furthermore, when the gate oxide is broken down, NIR light is emitted from the polysilicon/oxide/silicon structure. Optoelectronic characteristics of the device working in different modes are measured and compared. The mechanisms behind these different emissions are explored.展开更多
A neuronal signal detecting circuit and a neuronal signal stimulating circuit designed for a monolithic integrated MEA(micro-electrode array) system are described. As a basic cell of the circuits, an OPA( operation...A neuronal signal detecting circuit and a neuronal signal stimulating circuit designed for a monolithic integrated MEA(micro-electrode array) system are described. As a basic cell of the circuits, an OPA( operational amplifier) is designed with low power, low noise, small size and high gain. The detecting circuit has a chip area of 290 μm × 400 μm, a power dissipation of 2.02 mW, an equivalent input noise of 17.72 nV/ Hz, a gain of 60. 5 dB, and an output voltage from - 2. 48 to + 2. 5 V. The stimulating circuit has a chip area of 130 μm × 290 μm, a power dissipation of 740 μW, and an output voltage from - 2. 5 to 2. 04 V. The parameters show that two circuits are suitable for a monolithic integrated MEA system. The detecting circuit and MEA have been fabricated. The test results show that the detecting circuit works well.展开更多
A fully integrated class-E power amplifier(PA) at 2.4 GHz implemented in a 0. 18 μm 6-metal-layer mixed/RF CMOS ( complementary metal-oxide-semiconductor transistor ) technology is presented. A two-stage amplific...A fully integrated class-E power amplifier(PA) at 2.4 GHz implemented in a 0. 18 μm 6-metal-layer mixed/RF CMOS ( complementary metal-oxide-semiconductor transistor ) technology is presented. A two-stage amplification structure is chosen for this PA. The driving stage produces a high swing switch signal by using resonation technology. The output stage is designed as a class-E topology to realize the power amplification. Under a 1.2 V power supply, the PA delivers a maximum output power of 8. 8 dBm with a power-added efficiency (PAE) of 44%. A new power control method for the class-E power amplifier is described. By changing the amplitude and duty cycle of the signal which enters the class-E switch transistor, the output power can be covered from - 3 to 8. 8 dBm through a three-bit control word. The proposed PA can be used in low power applications, such as wireless sensor networks and biotelemetry systems.展开更多
The compact full custom layout design of a 16 kbit mask-programmable complementary metal oxide semiconductor (CMOS) read only memory (ROM) with low power dissipation is introduced. By optimizing storage cell size and ...The compact full custom layout design of a 16 kbit mask-programmable complementary metal oxide semiconductor (CMOS) read only memory (ROM) with low power dissipation is introduced. By optimizing storage cell size and peripheral circuit structure, the ROM has a small area of 0.050 mm2 with a power-delay product of 0.011 pJ/bit at +1.8 V. The high packing density and the excellent power-delay product have been achieved by using SMIC 0.18 μm 1P6M CMOS technology. A novel and simple sense amplifier/driver structure is presented which restores the signal full swing efficiently and reduces the signal rising time by 2.4 ns, as well as the memory access time. The ROM has a fast access time of 8.6 ns. As a consequence, the layout design not only can be embedded into microprocessor system as its program memory, but also can be fabricated individually as ROM ASIC.展开更多
基金Project supported by the National Natural Science Foundation of China(Grant Nos.60536030,61036002,60776024,60877035 and 61036009)National High Technology Research and Development Program of China(Grant Nos.2007AA04Z329 and 2007AA04Z254)
文摘A three-terminal silicon-based light emitting device is proposed and fabricated in standard 0.35 μm complementary metal-oxide-semiconductor technology. This device is capable of versatile working modes: it can emit visible to near infra-red (NIR) light (the spectrum ranges from 500 nm to 1000 nm) in reverse bias avalanche breakdown mode with working voltage between 8.35 V-12 V and emit NIR light (the spectrum ranges from 900 nm to 1300 nm) in the forward injection mode with working voltage below 2 V. An apparent modulation effect on the light intensity from the polysilicon gate is observed in the forward injection mode. Furthermore, when the gate oxide is broken down, NIR light is emitted from the polysilicon/oxide/silicon structure. Optoelectronic characteristics of the device working in different modes are measured and compared. The mechanisms behind these different emissions are explored.
基金The National Natural Science Foundation of China (No.90307013,90707005)the Natural Science Foundation of Jiangsu Province(No. BK2008032)Open Foundation of State Key Laboratory of Bio-Electronics of Southeast University
文摘A neuronal signal detecting circuit and a neuronal signal stimulating circuit designed for a monolithic integrated MEA(micro-electrode array) system are described. As a basic cell of the circuits, an OPA( operational amplifier) is designed with low power, low noise, small size and high gain. The detecting circuit has a chip area of 290 μm × 400 μm, a power dissipation of 2.02 mW, an equivalent input noise of 17.72 nV/ Hz, a gain of 60. 5 dB, and an output voltage from - 2. 48 to + 2. 5 V. The stimulating circuit has a chip area of 130 μm × 290 μm, a power dissipation of 740 μW, and an output voltage from - 2. 5 to 2. 04 V. The parameters show that two circuits are suitable for a monolithic integrated MEA system. The detecting circuit and MEA have been fabricated. The test results show that the detecting circuit works well.
基金The National High Technology Research and Development Program of China(863 Program)(No.2007AA01Z2A7)
文摘A fully integrated class-E power amplifier(PA) at 2.4 GHz implemented in a 0. 18 μm 6-metal-layer mixed/RF CMOS ( complementary metal-oxide-semiconductor transistor ) technology is presented. A two-stage amplification structure is chosen for this PA. The driving stage produces a high swing switch signal by using resonation technology. The output stage is designed as a class-E topology to realize the power amplification. Under a 1.2 V power supply, the PA delivers a maximum output power of 8. 8 dBm with a power-added efficiency (PAE) of 44%. A new power control method for the class-E power amplifier is described. By changing the amplitude and duty cycle of the signal which enters the class-E switch transistor, the output power can be covered from - 3 to 8. 8 dBm through a three-bit control word. The proposed PA can be used in low power applications, such as wireless sensor networks and biotelemetry systems.
文摘The compact full custom layout design of a 16 kbit mask-programmable complementary metal oxide semiconductor (CMOS) read only memory (ROM) with low power dissipation is introduced. By optimizing storage cell size and peripheral circuit structure, the ROM has a small area of 0.050 mm2 with a power-delay product of 0.011 pJ/bit at +1.8 V. The high packing density and the excellent power-delay product have been achieved by using SMIC 0.18 μm 1P6M CMOS technology. A novel and simple sense amplifier/driver structure is presented which restores the signal full swing efficiently and reduces the signal rising time by 2.4 ns, as well as the memory access time. The ROM has a fast access time of 8.6 ns. As a consequence, the layout design not only can be embedded into microprocessor system as its program memory, but also can be fabricated individually as ROM ASIC.