This paper presents two new efficient ternary Full Adder cells for nanoelectronics. These CNTFETbased ternary Full Adders are designed based on the unique characteristics of the CNTFET device, such as the capability o...This paper presents two new efficient ternary Full Adder cells for nanoelectronics. These CNTFETbased ternary Full Adders are designed based on the unique characteristics of the CNTFET device, such as the capability of setting the desired threshold voltages by adopting proper diameters for the nanotubes as well as the same carrier mobilities for the N-type and P-type devices. These characteristics of CNTFETs make them very suitable for designing high-performance multiple-Vth structures. The proposed structures reduce the number of the transistors considerably and have very high driving capability. The presented ternary Full Adders are simulated using Synopsys HSPICE with 32 nm CNTFET technology to evaluate their performance and to confirm their correct operation.展开更多
The design of a three-input logic circuit using carbon nanotube field effect transistors(CNTFETs)is presented.Ternary logic must be an exact replacement for dual logic since it performs straightforwardly in digital de...The design of a three-input logic circuit using carbon nanotube field effect transistors(CNTFETs)is presented.Ternary logic must be an exact replacement for dual logic since it performs straightforwardly in digital devices,which is why this design is so popular,and it also reduces chip area,both of which are examples of circuit overheads.The proposed module we have investigated is a triple-logic-based one,based on advanced technology CNTFETs and an emphasis on minimizing delay times at various values,as well as comparisons of the design working with various load capacitances.Comparing the proposed design with the existing design,the delay times was reduced from 66.32 to 16.41 ps,i.e.,a 75.26%reduction.However,the power dissipation was not optimized,and increased by 1.44%compared to the existing adder.The number of transistors was also reduced,and the product of power and delay(P∗D)achieved a value of 0.0498053 fJ.An improvement at 1 V was also achieved.A load capacitance(fF)was measured at different values,and the average delay measured for different values of capacitance had a maximum of 83.60 ps and a minimum of 22.54 ps,with a range of 61.06 ps.The power dissipations ranged from a minimum of 3.38μW to a maximum of 6.49μW.Based on these results,the use of this CNTFET half-adder design in multiple Boolean circuits will be a useful addition to circuit design.展开更多
基金supported by the Grant number 600/1792 from the vice presidency of research and technology of Shahid Beheshti University,G.C
文摘This paper presents two new efficient ternary Full Adder cells for nanoelectronics. These CNTFETbased ternary Full Adders are designed based on the unique characteristics of the CNTFET device, such as the capability of setting the desired threshold voltages by adopting proper diameters for the nanotubes as well as the same carrier mobilities for the N-type and P-type devices. These characteristics of CNTFETs make them very suitable for designing high-performance multiple-Vth structures. The proposed structures reduce the number of the transistors considerably and have very high driving capability. The presented ternary Full Adders are simulated using Synopsys HSPICE with 32 nm CNTFET technology to evaluate their performance and to confirm their correct operation.
文摘The design of a three-input logic circuit using carbon nanotube field effect transistors(CNTFETs)is presented.Ternary logic must be an exact replacement for dual logic since it performs straightforwardly in digital devices,which is why this design is so popular,and it also reduces chip area,both of which are examples of circuit overheads.The proposed module we have investigated is a triple-logic-based one,based on advanced technology CNTFETs and an emphasis on minimizing delay times at various values,as well as comparisons of the design working with various load capacitances.Comparing the proposed design with the existing design,the delay times was reduced from 66.32 to 16.41 ps,i.e.,a 75.26%reduction.However,the power dissipation was not optimized,and increased by 1.44%compared to the existing adder.The number of transistors was also reduced,and the product of power and delay(P∗D)achieved a value of 0.0498053 fJ.An improvement at 1 V was also achieved.A load capacitance(fF)was measured at different values,and the average delay measured for different values of capacitance had a maximum of 83.60 ps and a minimum of 22.54 ps,with a range of 61.06 ps.The power dissipations ranged from a minimum of 3.38μW to a maximum of 6.49μW.Based on these results,the use of this CNTFET half-adder design in multiple Boolean circuits will be a useful addition to circuit design.
