Overall plan and design of the task management system of ternary optical computer

t In this paper an overall scheme of the task management system of ternary optical computer （TOC） is proposed, and the software architecture chart is given. The function and accomplishment of each module in the system are described in general. In addition, according to the aforementioned scheme a prototype of TOC task management system is implemented, and the feasibility, rationality and completeness of the scheme are verified via running and testing the prototype.

Principle and architecture of parallel reconfiguration circuit for ternary optical computer

Reconfiguration is the key to produce an applicable ternary optical computer （TOC）. The method to implement the reconfiguration function determines whether a TOC can step into applied fields or not. In this work, a design of the reconfiguration circuit based on field programmable gates array （FPGA） is proposed, and the structure of the entire hardware system is discussed.

Principle of MSD floating-point division based on Newton-Raphson method on ternary optical computer

The division operation is not frequent relatively in traditional applications, but it is increasingly indispensable and important in many modern applications. In this paper, the implementation of modified signed-digit （MSD） floating-point division using Newton-Raphson method on the system of ternary optical computer （TOC） is studied. Since the addition of MSD floating-point is carry-free and the digit width of the system of TOC is large, it is easy to deal with the enough wide data and transform the division operation into multiplication and addition operations. And using data scan and truncation the problem of digits expansion is effectively solved in the range of error limit. The division gets the good results and the efficiency is high. The instance of MSD floating-point division shows that the method is feasible.

Decrease-radix design principle for carrying/borrowing free multi-valued and application in ternary optical computer

In this paper a new theory referred to as the decrease-radix design （DRD） is proposed, which is found in the research of logic units of ternary （tri-valued） optical computer. Based on the theory proposed, the principles and the regulations of the DRD for making operation units of multi-valued operation with carrying/borrowing free are also presented. The research work has come to the following important conclusion： let D be a special state contained in n physical informative states, then one may figure out any multi-valued processors within n^（n×n） carrying/borrowing free n-valued units by the composition some of n×n×（n-1） simplest basic operating units according to the regulations of DRD proposed in this paper. The detailed systematic way of our design regulations is highlighted step by step in the paper with an example of design of a tri-valued logic optical operating unit. The real architecture, the procedure, and the experimental results of our sample in tri-valued logic operating unit are given. Finally, a re-constructible model of ternary logical optical processor is introduced. The theory proposed in the paper has laid down a solid foundation for the design of re-constructible carrying/borrowing free operating units in ternary optical computers and can be widely used as the designing reference in a variety of multi-valued logic operating units.

Ternary optical computer principle

The fundamental principle and the characteristics of ternary optical computer, using horizontal polarized light, vertical polarized light and no-intensity to express information, are propounded in this paper. The practicability to make key parts of the ternary optical computer from modern micro or integrated optical devices, opto-electronic and electro-photonic elements is discussed. The principle can be applied in three-state optical fiber communication via horizontal and vertical polarized light.

Experimentation of a 1-pixel bit reconfigurable ternary optical processor

A detailed experiment of 1-pixel bit reconfigurable ternary optical processor （TOP） is proposed in the paper. 42 basic operation units （BOUs） and 28 typical logic operators of the TOP are realized in the experiment. Results of the test cases elaborately cover the every combination of BOUs and all the nine inputs of ternary processor. Both the experiment process and results analysis are given in this paper. The experimental results demonstrate that the theory of reconfiguring a TOP is valid and that the reconfiguration circuitry is effective.