Influence of Tilted Angle on Effective Linear Energy Transfer in Single Event Effect Tests for Integrated Circuits at 130 nm Technology Node

A heavy-ion irradiation experiment is studied in digital storage cells with different design approaches in 130？nm CMOS bulk Si and silicon-on-insulator （SOI） technologies. The effectiveness of linear energy transfer （LET） with a tilted ion beam at the 130？nm technology node is obtained. Tests of tilted angles θ=0 ° , 30 ° and 60 ° with respect to the normal direction are performed under heavy-ion Kr with certain power whose LET is about 40？MeVcm 2 /mg at normal incidence. Error numbers in D flip-flop chains are used to determine their upset sensitivity at different incidence angles. It is indicated that the effective LETs for SOI and bulk Si are not exactly in inverse proportion to cosθ , furthermore the effective LET for SOI is more closely in inverse proportion to cosθ compared to bulk Si, which are also the well known behavior. It is interesting that, if we design the sample in the dual interlocked storage cell approach, the effective LET in bulk Si will look like inversely proportional to cosθ very well, which is also specifically explained.

Chair's Introduction to 2009 IEEE Circuits and Systems International Conference on Testing and Diagnosis

Based on the recommendation of ICTD＇09 TPC members, this Special Issue of the Journal of Electronic Science ＆ Technology of China （JESTC） contained 22 high quality papers selected from the Proceedings of 2009 IEEE Circuits and Systems International Conference on Testing and Diagnosis （ICTD ＇09） which is fully sponsored by the IEEE Circuits and Systems Society （CASS）, and is technically co-sponsored by the University of Electronic Science and Technology of China （UESTC）, the Chinese Institute of Electronics （CIE）, the China Instrument ＆ Control Society （CIS）, and organized by UESTC.

A Radial Stub Test Circuit for Microwave Power Devices

With the principles of microwave circuits and semiconductor device physics, two microwave power device test circuits combined with a test fixture are designed and simulated, whose properties are evaluated by a parameter network analyzer within the frequency range from 3 to 8GHz. The simulation and experimental results verify that the test circuit with a radial stub is better than that without. As an example, a C-band AlGaN/GaN HEMT microwave power device is tested with the designed circuit and fixture. With a 5.4GHz microwave input signal,the maximum gain is 8.75dB,and the maximum output power is 33.2dBm.

TEST OF BOARD-LEVEL BOUNDARY SCAN INTEGRITY

The IEEE Standard 1149.1 boundary scan (BS) implementation provides the internal access required for testing the digital printed circuit board (PCB). However, the integrity of the boundary scan test infrastructure should be tested first to guarantee the validation of the results of the rest functional test and diagnosis. This paper describes the fault models and test principles of the BS test access port (TAP) lines on PCBs. A test algorithm with high fault coverage and short time is then presented for the PCB on which all ICs are BS ones.

General Consideration of Measuring System for Operational Test of Thyristor Valves of Ultra High Voltage DC Power Transmission

Thyristor valve is one of the key equipments for ultra high voltage direct current(UHVDC) power transmission projects.Before being installed on site,they need to be tested in a laboratory in order to verify their operational performance to satisfy the technical specification of project related.Test facilities for operational tests of thyristor valves are supposed to enable to undertake more severe electrical stresses than those being applied in the thyristor valves under test(test objects).On the other hand,the stresses applied into the test objects are neither higher nor lower than specified by the specification,because inappropriate stresses applied would result in incorrect evaluation of performance on the test objects,more seriously,would cuase the damage of test objects with expensive cost losing.Generally,the process of operational tests is complicated and performed in a complex synthetic test circuit(hereafter as STC),where there are a lot of sensors used for measuring,monitoring and protection on line to ensure that the test circuit functions in good condition.Therefore,the measuring systems embedded play a core role in STC,acting like "eyes".Based on the first project of building up a STC in China,experience of planning measuring systems is summarized so as to be referenced by related engineers.

Investigation into Equivalency of Synthetic Test Circuit Used for Operational Tests of Thyristor Valves for UHVDC

With the growth of capacity of high voltage direct current(HVDC) transmission lines,the ratings of thyristor valves,which are one of the most critical equipments,are getting higher and higher.Verification of performance of thyristor valves particularly designed for HVDC project plays an important role in the handover of products between the manufacturer and the client.Conventional test facilities based on philosophy of direct test cannot meet the requirements for modern thyristor valves.New test facilities with high ratings are necessarily built based on philosophy of synthetic test.Over the conventional direct test circuit,the later is an economical and feasible solution with less financial investment and higher test capability.However,the equivalency between the synthetic test and the direct test should be analyzed technically in order to make sure that the condition of verification test in a synthetic test circuit should satisfy the actual operation condition of thyristor valves existing in a real HVDC project,just as in a direct test circuit.Equivalency analysis is focused in this paper,covering the scope of thyristor valves' steady state,and transient state.On the basis of the results achieved,a synthetic test circuit of 6 500 A/50 kV for operational tests of thyristor valves used for up to UHVDC project has newly been set up and already put into service in Xi'an High Voltage Apparatus Research Institute Co.,Ltd.(XIHARI),China.Some of the results have been adopted also by a new national standard of China.

Test Vector Optimization Using Pocofan-Poframe Partitionin

This paper presents an automated POCOFAN-POFRAME algorithm thatpartitions large combinational digital VLSI circuits for pseudo exhaustive testing. In thispaper, a simulation framework and partitioning technique are presented to guide VLSIcircuits to work under with fewer test vectors in order to reduce testing time and todevelop VLSI circuit designs. This framework utilizes two methods of partitioningPrimary Output Cone Fanout Partitioning (POCOFAN) and POFRAME partitioning todetermine number of test vectors in the circuit. The key role of partitioning is to identifyreconvergent fanout branch pairs and the optimal value of primary input node N andfanout F partitioning using I-PIFAN algorithm. The number of reconvergent fanout andits locations are critical for testing of VLSI circuits and design for testability. Hence, theirselection is crucial in order to optimize system performance and reliability. In the presentwork, the design constraints of the partitioned circuit considered for optimizationincludes critical path delay and test time. POCOFAN-POFRAME algorithm uses theparameters with optimal values of circuits maximum primary input cone size (N) andminimum fan-out value (F) to determine the number of test vectors, number of partitionsand its locations. The ISCAS’85 benchmark circuits have been successfully partitioned,the test results of C499 shows 45% reduction in the test vectors and the experimentalresults are compared with other partitioning methods, our algorithm makes fewer testvectors.

VST/DL Digital Circuit Testing & Analytical System

An important means for digital circuit analysis, design. maintenance and production is the IC chip test and analysis. With digital circuit application prevailing today, the automatic test and analysis of digital circuits is going to play a more important role. It can save a great deal of time and cost for the maintenance of equipment and can also provide correst analytical data for designers.

RELIABILITY OF TEST LANDS TARGETING IN BED-OF-NAILS STYLE TEST FIXTURE

A systematic, accurate and robust evaluating method for fine pitch printed circuit board （PCB） positioning assessment in testing fixture is developed. Targeting reliability of bed-of-nails tester is successfully evaluated by the 2D pattern transform. Probe offset vector with its Weibull and Gaussian distribution estimates are obtained for further investigation about the causes of misalignment on the basis of a batch tests for same kind of PCBs.

Predicting stability of integrated circuit test equipment using upper side boundary values of normal distribution

In response to the growing complexity and performance of integrated circuit(IC),there is an urgent need to enhance the testing and stability of IC test equipment.A method was proposed to predict equipment stability using the upper side boundary value of normal distribution.Initially,the K-means clustering algorithm classifies and analyzes sample data.The accuracy of this boundary value is compared under two common confidence levels to select the optimal threshold.A range is then defined to categorize unqualified test data.Through experimental verification,the method achieves the purpose of measuring the stability of qualitative IC equipment through a deterministic threshold value and judging the stability of the equipment by comparing the number of unqualified data with the threshold value,which realizes the goal of long-term operation monitoring and stability analysis of IC test equipment.

Ethernet Controller SoC Design and Its Low-Power DFT Considerations

In this paper, an Ethernet controller SoC solution and its low power design for testability （DFT） for information appliances are presented. On a single chip, an enhanced one-cycle 8-bit micro controller unit （MCU）, media access control （MAC） circuit and embedded memories such as static random access memory （SRAM）, read only memory （ROM） and flash are all integrated together. In order to achieve high fault coverage, at the same time with low test power, different DFT techniques are adopted for different circuits： the scan circuit that reduces switching activity is implemented for digital logic circuits; BIST-based method is employed for the on-chip SRAM and ROM. According to the fault-modeling of embedded flash, we resort to a March-like method for flash built in self test （BIST）. By all means above, the result shows that the fault coverage may reach 97%, and the SoC chip is implemented successfully by using 0.25 μm two-poly four-metal mixed signal complementary metal oxide semiconductor （CMOS） technology, the die area is 4.8×4.6 mm^2. Test results show that the maximum throughput of Ethemet packets may reach 7Mb·s^1.

Pseudo-Random Test Generation for Large Combinational Circuits

In this paper,a simulation system of pseudo-random testing is described first to investigate the characteristics of pseudo-random testing.Several interesting experimental results are obtained.It is found out that initial states of pseudo-random sequences have little effect on fault coverage.Fixed connection between LFSR outputs and circuit inputs in which the number of LFSR stages m is less than the number of circuit inputs n leads to low fault coverage,and the fault coverage is reduced as m decreases.The local unrandomness of pseudo-random sequences is exposed clearly.Generally,when an LFSR is employed as a pseudo-random generator,there are at least as many LFSR stages as circuit inputs.However,for large circuits under test with hundreds of inputs,there are drawbacks of using an LFSR with hundreds of stages.In the paper,a new design for a pseudo-random pattern generator is proposed in which m<n.The relationship between test length and the number of LFSR stages is discussed in order to obtain necessary,fault coverage.It is shown that the design cannot only save LFSR hardware but also reduce test length without loss of fault coverage,and is easy to implement. The experimental results are provided for the 10 Benchmark Circuits to show the effectiveness of the generator.

A Complete Critical Path Algorithm for Test Generation of Combinational Circuits

It is known that critical path test generation method is not a complete algorithm for combinational circuits with reconvergent-fanout.In order to make it a complete algorithm,we put forward a reconvergent-fanout- oriented technique,the principal critical path algorithm,propagating the critical value back to primary inputs along a single path,the principal critical path,and allowing multiple path sensitization if needed.Relationship among test patterns is also discussed to accelerate test generation.