Diagnosing intermittent fault is an important approach to reduce built-in test（BIT） false alarms. Aiming at solving the shortcoming of the present diagnostic method of intermittent fault, and according to the merit ...Diagnosing intermittent fault is an important approach to reduce built-in test（BIT） false alarms. Aiming at solving the shortcoming of the present diagnostic method of intermittent fault, and according to the merit of support vector machines （ SVM） which can be trained with a small-sample, an SVM-based diagnostic model of 3 states that include OK state, intermittent state and faulty state is presented. With the features based on the reflection coefficients of an alarm rate （ AR ） model extracted from small vibration samples, these models are trained to diagnose intermittent faults. The experimental results show that this method can diagnose multiple intermittent faults accurately with small training samples and BIT false alarms are reduced.展开更多
This paper presents modified version of a realistic test tool suitable to Design For Testability （DFT） and Built-ln Self Test （BIST） environments. A comprehensive tool is developed in the form of a test simulator....This paper presents modified version of a realistic test tool suitable to Design For Testability （DFT） and Built-ln Self Test （BIST） environments. A comprehensive tool is developed in the form of a test simulator. The simulator is capable of providing a required goal of test for the Circuit Under Test （CUT）. The simulator uses the approach of fault diagnostics with fault grading procedures to provide the optimum tests. The current version of the simulator embeds features of exhaustive and pseudo-random test generation schemes along with the search solutions of cost effective test goals. The simulator provides facilities of realizing all possible pseudo-random sequence generators with all possible combinations of seeds. The tool is developed on a common Personal Computer （PC） platform and hence no special software is required. Thereby, it is a low cost tool hence economical. The tool is very much suitable for determining realistic test sequences for a targeted goal of testing for any CUT. The developed tool incorporates flexible Graphical User Interface （GUI） procedures and can be operated without any special programming skill. The tool is debugged and tested with the results of many bench mark circuits. Further, this developed tool can be utilized for educational purposes for many courses such as fault-tolerant computing, fault diagnosis, digital electronics, and safe-reliable-testable digital logic designs.展开更多
随着智能网联车辆技术的迅速发展,汽车自动化程度越来越高,当总线网络需要更多数量的电子控制单元(ECU,electronic control unit),车载总线的布局越来越复杂时,传统搭建车载总线测试台架效率较低、通用性差,不能满足主机厂测试需求.通...随着智能网联车辆技术的迅速发展,汽车自动化程度越来越高,当总线网络需要更多数量的电子控制单元(ECU,electronic control unit),车载总线的布局越来越复杂时,传统搭建车载总线测试台架效率较低、通用性差,不能满足主机厂测试需求.通过深入研究车载控制器局域网(CAN,controller area network)总线的测试,分析了传统测试台架的缺点,提出了一种基于Vector工具链车载CAN总线自动化测试系统.该系统通过Vector工具链之间的功能联系,采用能被CAPL语言调用的C++语言开发的底层驱动,以实现车载CAN总线、LIN(local interconnect network)总线自动化测试.本文设计了与人工测试的对比实验,验证了该系统不仅能解决车载总线测试通用性差的缺点,而且还提高了测试效率.展开更多
文摘Diagnosing intermittent fault is an important approach to reduce built-in test（BIT） false alarms. Aiming at solving the shortcoming of the present diagnostic method of intermittent fault, and according to the merit of support vector machines （ SVM） which can be trained with a small-sample, an SVM-based diagnostic model of 3 states that include OK state, intermittent state and faulty state is presented. With the features based on the reflection coefficients of an alarm rate （ AR ） model extracted from small vibration samples, these models are trained to diagnose intermittent faults. The experimental results show that this method can diagnose multiple intermittent faults accurately with small training samples and BIT false alarms are reduced.
文摘This paper presents modified version of a realistic test tool suitable to Design For Testability （DFT） and Built-ln Self Test （BIST） environments. A comprehensive tool is developed in the form of a test simulator. The simulator is capable of providing a required goal of test for the Circuit Under Test （CUT）. The simulator uses the approach of fault diagnostics with fault grading procedures to provide the optimum tests. The current version of the simulator embeds features of exhaustive and pseudo-random test generation schemes along with the search solutions of cost effective test goals. The simulator provides facilities of realizing all possible pseudo-random sequence generators with all possible combinations of seeds. The tool is developed on a common Personal Computer （PC） platform and hence no special software is required. Thereby, it is a low cost tool hence economical. The tool is very much suitable for determining realistic test sequences for a targeted goal of testing for any CUT. The developed tool incorporates flexible Graphical User Interface （GUI） procedures and can be operated without any special programming skill. The tool is debugged and tested with the results of many bench mark circuits. Further, this developed tool can be utilized for educational purposes for many courses such as fault-tolerant computing, fault diagnosis, digital electronics, and safe-reliable-testable digital logic designs.
文摘随着智能网联车辆技术的迅速发展,汽车自动化程度越来越高,当总线网络需要更多数量的电子控制单元(ECU,electronic control unit),车载总线的布局越来越复杂时,传统搭建车载总线测试台架效率较低、通用性差,不能满足主机厂测试需求.通过深入研究车载控制器局域网(CAN,controller area network)总线的测试,分析了传统测试台架的缺点,提出了一种基于Vector工具链车载CAN总线自动化测试系统.该系统通过Vector工具链之间的功能联系,采用能被CAPL语言调用的C++语言开发的底层驱动,以实现车载CAN总线、LIN(local interconnect network)总线自动化测试.本文设计了与人工测试的对比实验,验证了该系统不仅能解决车载总线测试通用性差的缺点,而且还提高了测试效率.
