Air leakage in underground coal mines presents a serious hazard for coal production and the safety of miners.Coating technology is commonly used as an efficient means for preventing air leakage.To address existing pro...Air leakage in underground coal mines presents a serious hazard for coal production and the safety of miners.Coating technology is commonly used as an efficient means for preventing air leakage.To address existing problems with high dust concentrations in large operations involving complex processes and the high cost of traditional coating technology,a novel coating technology that ensures intrinsic safety by utilizing water pressure and wind pressure was developed.This new coating technology was designed to suction and spray,and the technical parameters of its spray performance was also studied.The experimental tests and evaluation indicated the optimum working range is 0.3–0.7 MPa of wind pressure,1.2–10.2 L/min of water quantity,and 1.0–3.5 m of spraying distance.Moreover,this novel coating technology was tested in the Dashuitou Coal Mine in Gansu Province of China.Compared with conventional counterparts,the proposed new technology is safe,efficient,and convenient to operate.During spraying,dust concentrations were kept at less than 10 mg/m3,and the average rebound ratio resilient rate of solid materials was below 13%.After spraying,the average leakage every 100 m was 4 m3/min,and the oxygen volume fraction in the adjacent goaf was approximately 4%,demonstrating excellent air leakage prevention.展开更多
Silicon-on-insulator (SOI) CMOS technology is a very attractive option for implementing digital integrated circuits for low power applications. This paper presents migration of standby subthreshold leakage control tec...Silicon-on-insulator (SOI) CMOS technology is a very attractive option for implementing digital integrated circuits for low power applications. This paper presents migration of standby subthreshold leakage control technique from a bulk CMOS to SOI CMOS technology. An improved SOI CMOS technology based circuit technique for effective reduction of standby subthreshold leakage power dissipation is proposed in this paper. The proposed technique is validated through design and simulation of a one-bit full adder circuit at a temperature of 27℃, supply voltage, VDD of 0.90 V in 120 nm SOI CMOS technology. Existing standby subthreshold leakage control techniques in CMOS bulk technology are compared with the proposed technique in SOI CMOS technology. Both the proposed and existing techniques are also implemented in SOI CMOS technology and compared. Reduction in standby subthreshold leakage power dissipation by reduction factors of 54x and 45x foraone-bit full adder circuit was achieved using our proposed SOI CMOS technology based circuit technique in comparison with existing techniques such as MTCMOS technique and SCCMOS technique respectively in CMOS bulk technology. Dynamic power dissipation was also reduced significantly by using this proposed SOI CMOS technology based circuit technique. Standby subthreshold leakage power dissipation and dynamic power dissipation were also reduced significantly using the proposed circuit technique in comparison with other existing techniques, when all circuit techniques were implemented in SOI CMOS technology. All simulations were performed using Microwindver 3.1 EDA tool.展开更多
In order to reduce the risk of spontaneous combustion in goaf during goaf excavation process, polymer modified cement mortar spraying material was used to spray and seal the roadway surface. The experimental applicati...In order to reduce the risk of spontaneous combustion in goaf during goaf excavation process, polymer modified cement mortar spraying material was used to spray and seal the roadway surface. The experimental application was carried out in the upper channel 2304 of a mine in Henan Province. The test results showed that polymer modified cement mortar spraying material could effectively support the roadway and greatly reduce the deformation rate of the roadway. The best spraying thickness is 5 mm. Through the monitoring of tunnel air leakage, it is concluded that the polymer modified cement mortar spraying material can reduce the tunnel air leakage and play a better sealing effect.展开更多
A design of a high-speed multi-core processor with compact size is a trending approach in the Integrated Circuits(ICs)fabrication industries.Because whenever device size comes down into narrow,designers facing many po...A design of a high-speed multi-core processor with compact size is a trending approach in the Integrated Circuits(ICs)fabrication industries.Because whenever device size comes down into narrow,designers facing many power den-sity issues should be reduced by scaling threshold voltage and supply voltage.Initially,Complementary Metal Oxide Semiconductor(CMOS)technology sup-ports power saving up to 32 nm gate length,but further scaling causes short severe channel effects such as threshold voltage swing,mobility degradation,and more leakage power(less than 32)at gate length.Hence,it directly affects the arithmetic logic unit(ALU),which suffers a significant power density of the scaled multi-core architecture.Therefore,it losses reliability features to get overheating and increased temperature.This paper presents a novel power mini-mization technique for active 4-bit ALU operations using Fin Field Effect Tran-sistor(FinFET)at 22 nm technology.Based on this,a diode is directly connected to the load transistor,and it is active only at the saturation region as a function.Thereby,the access transistor can cutoff of the leakage current,and sleep transis-tors control theflow of leakage current corresponding to each instant ALU opera-tion.The combination of transistors(access and sleep)reduces the leakage current from micro to nano-ampere.Further,the power minimization is achieved by con-necting the number of transistors(6T and 10T)of the FinFET structure to ALU with 22 nm technology.For simulation concerns,a Tanner(T-Spice)with 22 nm technology implements the proposed design,which reduces threshold vol-tage swing,supply power,leakage current,gate length delay,etc.As a result,it is quite suitable for the ALU architecture of a high-speed multi-core processor.展开更多
基金supported by the National Natural Science Foundation of China(Grant No.51704283)Natural Science Foundation of Jiangsu Province(BK20170277)+1 种基金Program for Changjiang Scholars and Innovative Research Team in University(IRT_17R103)the Fundamental Research Funds for the Central Universities(2014XT02)。
文摘Air leakage in underground coal mines presents a serious hazard for coal production and the safety of miners.Coating technology is commonly used as an efficient means for preventing air leakage.To address existing problems with high dust concentrations in large operations involving complex processes and the high cost of traditional coating technology,a novel coating technology that ensures intrinsic safety by utilizing water pressure and wind pressure was developed.This new coating technology was designed to suction and spray,and the technical parameters of its spray performance was also studied.The experimental tests and evaluation indicated the optimum working range is 0.3–0.7 MPa of wind pressure,1.2–10.2 L/min of water quantity,and 1.0–3.5 m of spraying distance.Moreover,this novel coating technology was tested in the Dashuitou Coal Mine in Gansu Province of China.Compared with conventional counterparts,the proposed new technology is safe,efficient,and convenient to operate.During spraying,dust concentrations were kept at less than 10 mg/m3,and the average rebound ratio resilient rate of solid materials was below 13%.After spraying,the average leakage every 100 m was 4 m3/min,and the oxygen volume fraction in the adjacent goaf was approximately 4%,demonstrating excellent air leakage prevention.
文摘Silicon-on-insulator (SOI) CMOS technology is a very attractive option for implementing digital integrated circuits for low power applications. This paper presents migration of standby subthreshold leakage control technique from a bulk CMOS to SOI CMOS technology. An improved SOI CMOS technology based circuit technique for effective reduction of standby subthreshold leakage power dissipation is proposed in this paper. The proposed technique is validated through design and simulation of a one-bit full adder circuit at a temperature of 27℃, supply voltage, VDD of 0.90 V in 120 nm SOI CMOS technology. Existing standby subthreshold leakage control techniques in CMOS bulk technology are compared with the proposed technique in SOI CMOS technology. Both the proposed and existing techniques are also implemented in SOI CMOS technology and compared. Reduction in standby subthreshold leakage power dissipation by reduction factors of 54x and 45x foraone-bit full adder circuit was achieved using our proposed SOI CMOS technology based circuit technique in comparison with existing techniques such as MTCMOS technique and SCCMOS technique respectively in CMOS bulk technology. Dynamic power dissipation was also reduced significantly by using this proposed SOI CMOS technology based circuit technique. Standby subthreshold leakage power dissipation and dynamic power dissipation were also reduced significantly using the proposed circuit technique in comparison with other existing techniques, when all circuit techniques were implemented in SOI CMOS technology. All simulations were performed using Microwindver 3.1 EDA tool.
文摘In order to reduce the risk of spontaneous combustion in goaf during goaf excavation process, polymer modified cement mortar spraying material was used to spray and seal the roadway surface. The experimental application was carried out in the upper channel 2304 of a mine in Henan Province. The test results showed that polymer modified cement mortar spraying material could effectively support the roadway and greatly reduce the deformation rate of the roadway. The best spraying thickness is 5 mm. Through the monitoring of tunnel air leakage, it is concluded that the polymer modified cement mortar spraying material can reduce the tunnel air leakage and play a better sealing effect.
文摘A design of a high-speed multi-core processor with compact size is a trending approach in the Integrated Circuits(ICs)fabrication industries.Because whenever device size comes down into narrow,designers facing many power den-sity issues should be reduced by scaling threshold voltage and supply voltage.Initially,Complementary Metal Oxide Semiconductor(CMOS)technology sup-ports power saving up to 32 nm gate length,but further scaling causes short severe channel effects such as threshold voltage swing,mobility degradation,and more leakage power(less than 32)at gate length.Hence,it directly affects the arithmetic logic unit(ALU),which suffers a significant power density of the scaled multi-core architecture.Therefore,it losses reliability features to get overheating and increased temperature.This paper presents a novel power mini-mization technique for active 4-bit ALU operations using Fin Field Effect Tran-sistor(FinFET)at 22 nm technology.Based on this,a diode is directly connected to the load transistor,and it is active only at the saturation region as a function.Thereby,the access transistor can cutoff of the leakage current,and sleep transis-tors control theflow of leakage current corresponding to each instant ALU opera-tion.The combination of transistors(access and sleep)reduces the leakage current from micro to nano-ampere.Further,the power minimization is achieved by con-necting the number of transistors(6T and 10T)of the FinFET structure to ALU with 22 nm technology.For simulation concerns,a Tanner(T-Spice)with 22 nm technology implements the proposed design,which reduces threshold vol-tage swing,supply power,leakage current,gate length delay,etc.As a result,it is quite suitable for the ALU architecture of a high-speed multi-core processor.
