Atomic layer deposition for nanoscale oxide semiconductor thin film transistors:review and outlook

Since the first report of amorphous In–Ga–Zn–O based thin film transistors,interest in oxide semiconductors has grown.They offer high mobility,low off-current,low process temperature,and wide flexibility for compositions and processes.Unfortunately,depositing oxide semiconductors using conventional processes like physical vapor deposition leads to problematic issues,especially for high-resolution displays and highly integrated memory devices.Conventional approaches have limited process flexibility and poor conformality on structured surfaces.Atomic layer deposition(ALD)is an advanced technique which can provide conformal,thickness-controlled,and high-quality thin film deposition.Accordingly,studies on ALD based oxide semiconductors have dramatically increased recently.Even so,the relationships between the film properties of ALD-oxide semiconductors and the main variables associated with deposition are still poorly understood,as are many issues related to applications.In this review,to introduce ALD-oxide semiconductors,we provide:(a)a brief summary of the history and importance of ALD-based oxide semiconductors in industry,(b)a discussion of the benefits of ALD for oxide semiconductor deposition(in-situ composition control in vertical distribution/vertical structure engineering/chemical reaction and film properties/insulator and interface engineering),and(c)an explanation of the challenging issues of scaling oxide semiconductors and ALD for industrial applications.This review provides valuable perspectives for researchers who have interest in semiconductor materials and electronic device applications,and the reasons ALD is important to applications of oxide semiconductors.

Homojunction structure amorphous oxide thin film transistors with ultra-high mobility

Amorphous oxide semiconductors(AOS)have unique advantages in transparent and flexible thin film transistors(TFTs)applications,compared to low-temperature polycrystalline-Si(LTPS).However,intrinsic AOS TFTs are difficult to obtain field-effect mobility(μFE)higher than LTPS(100 cm^(2)/(V·s)).Here,we design ZnAlSnO(ZATO)homojunction structure TFTs to obtainμFE=113.8 cm^(2)/(V·s).The device demonstrates optimized comprehensive electrical properties with an off-current of about1.5×10^(-11)A,a threshold voltage of–1.71 V,and a subthreshold swing of 0.372 V/dec.There are two kinds of gradient coupled in the homojunction active layer,which are micro-crystallization and carrier suppressor concentration gradient distribution so that the device can reduce off-current and shift the threshold voltage positively while maintaining high field-effect mobility.Our research in the homojunction active layer points to a promising direction for obtaining excellent-performance AOS TFTs.

Fabrication of Bottom-Gate and Top-Gate Transparent ZnO Thin Film Transistors

Transparent zinc oxide thin film transistors （ZnO-TFTs） with bottom-gate and top-gate structures were constructed on 50mm silica glass substrates. The ZnO films were deposited by RF magnetron sputtering and SiO2 films served as the gate insulator layer. We found that the ZnO-TFTs with bottom-gate structure have better electrical performance than those with top-gate structure. The bottom-gate ZnO-TFTs operate as an n-channel enhancement mode, which have clear pinch off and saturation characteristics. The field effect mobility, threshold voltage, and the current on/off ratio were determined to be 18.4cm^2/（V ·s）, - 0. 5V and 10^4 , respectively. Meanwhile, the top-gate ZnO-TFTs exhibit n-chan- nel depletion mode operation and no saturation characteristics were detected. The electrical difference of the devices may be due to the different character of the interface between the channel and insulator layers. The two transistors types have high transparency in the visible light region.

Influence of High Temperature Treatment on the Performance of Nickel-Induced Laterally Crystallized Thin Film Transistors

Well known for their good performance,thin film transistors (TFTs) with active layers which were nickel induced laterally crystallized,are fabricated by conventional process of dual gate CMOS.The influence of pre high temperature treatment of device fabrication on the performance of TFTs is also investigated.The experiment shows that the high temperature treatment affects the performance of the devices strongly.The best performance is obtained by adopting pre treatment of 1000℃.The mobility of 314cm 2/(V·s) is obtained at NMOS TFTs with pre treatment of 1000℃,which is 10% and 22% higher than that treated at 1100℃ and without pre high temperature treatment,respectively.A maximum on/off current ratio of 3×10 8 is also obtained at 1000℃.Further investigation of uniformity verifies that the result is reliable.

Simulation of grain boundary effect on characteristics of ZnO thin film transistor by considering the location and orientation of grain boundary

The grain boundaries （GBs） have a strong effect on the electric properties of ZnO thin film transistors （TFTs）. A novel grain boundary model was developed to analyse the effect. The model was characterized with different angles between the orientation of the grain boundary and the channel direction. The potential barriers formed by the grain boundaries increase with the increase of the grain boundary angle, so the degradation of the transistor characteristics increases. When a grain boundary is close to the drain edge, the potential barrier height reduces, so the electric properties were improved.

Carrier Transport Across Grain Boundaries in Polycrystalline Silicon Thin Film Transistors

We established a model for investigating polycrystalline silicon（poly-Si） thin film transistors（TFTs）.The effect of grain boundaries（GBs） on the transfer characteristics of TFT was analyzed by considering the number and the width of grain boundaries in the channel region,and the dominant transport mechanism of carrier across grain boundaries was subsequently determined.It is shown that the thermionic emission（TE） is dominant in the subthreshold operating region of TFT regardless of the number and the width of grain boundary.To a poly-Si TFT model with a 1 nm-width grain boundary,in the linear region,thermionic emission is similar to that of tunneling（TU）,however,with increasing grain boundary width and number,tunneling becomes dominant.

Influence of white light illumination on the performance of a-IGZO thin film transistor under positive gate-bias stress

The influence of white light illumination on the stability of an amorphous In GaZnO thin film transistor is investigated in this work. Under prolonged positive gate bias stress, the device illuminated by white light exhibits smaller positive threshold voltage shift than the device stressed under dark. There are simultaneous degradations of field-effect mobility for both stressed devices, which follows a similar trend to that of the threshold voltage shift. The reduced threshold voltage shift under illumination is explained by a competition between bias-induced interface carrier trapping effect and photon-induced carrier detrapping effect. It is further found that white light illumination could even excite and release trapped carriers originally exiting at the device interface before positive gate bias stress, so that the threshold voltage could recover to an even lower value than that in an equilibrium state. The effect of photo-excitation of oxygen vacancies within the a-IGZO film is also discussed.

Properties of C_(60) thin film transistor based on polystyrene

This paper reports that the n-type organic thin-fihn transistors have been fabricated by using C60 as the active layer and polystyrene as the dielectric. The properties of insulator and the growth characteristic of C60 film were carefully investigated. By choosing different source/drain electrodes, a device with good performance can be obtained. The highest electron field effect mobility about 1.15 cm2/（V. s） could reach when Barium was introduced as electrodes. Moreover, the C60 transistor shows a negligible ＇hysteresis effect＇ contributed to the hydroxyl-free of insulator. The result suggests that polymer dielectrics are promising in applications among n-type organic transistors.

Degradation of current–voltage and low frequency noise characteristics under negative bias illumination stress in InZnO thin film transistors

The instabilities of indium–zinc oxide thin film transistors under bias and/or illumination stress are studied in this paper. Firstly, illumination experiments are performed, which indicates the variations of current–voltage characteristics and electrical parameters（such as threshold voltage and sub-threshold swing） are dominated by the stress-induced ionized oxygen vacancies and acceptor-like states. The dependence of degradation on light wavelength is also investigated. More negative shift of threshold voltage and greater sub-threshold swing are observed with the decrease of light wavelength.Subsequently, a negative bias illumination stress experiment is carried out. The degradation of the device is aggravated due to the decrease of recombination effects between ionized oxygen vacancies and free carriers. Moreover, the contributions of ionized oxygen vacancies and acceptor-like states are separated by using the mid-gap method. In addition, ionized oxygen vacancies are partially recombined at room temperature and fully recombined at high temperature. Finally, low-frequency noise is measured before and after negative bias illumination stress. Experimental results show few variations of the oxide trapped charges are generated during stress, which is consistent with the proposed mechanism.

Positive gate bias stress-induced hump-effect in elevated-metal metal-oxide thin film transistors

Under the action of a positive gate bias stress, a hump in the subthreshold region of the transfer characteristic is observed for the amorphous indium-gallium-zinc oxide thin film transistor, which adopts an elevated-metal metal-oxide structure. As stress time goes by, both the on-state current and the hump shift towards the negative gate-voltage direction. The humps occur at almost the same current levels for devices with different channel widths, which is attributed to the parasitic transistors located at the channel width edges. Therefore, we propose that the positive charges trapped at the back-channel interface cause the negative shift, and the origin of the hump is considered as being due to more positive charges trapped at the edges along the channel width direction. On the other hand, the hump-effect becomes more significant in a short channel device （L=2 μm）. It is proposed that the diffusion of oxygen vacancies takes place from the high concentration source/drain region to the intrinsic channel region.

Performance improvement in pentacene organic thin film transistors by inserting a C_(60) ultrathin layer

The contact effect on the performances of organic thin film transistors is studied here. A C60 ultrathin layer is inserted between Al source-drain electrode and pentacene to reduce the contact resistance. By a 3 nm C60 modification, the injection barrier is lowered and the contact resistance is reduced. Thus, the field-effect mobility increases from 0.12 to 0.52 cm2/（V.s）. It means that inserting a C60 ultra thin layer is a good method to improve the organic thin film transistor （OTFT） performance. The output curve is simulated by using a charge drift model. Considering the contact effect, the field effect mobility is improved to 1.15 cm2/（V-s）. It indicates that further reducing the contact resistance of OTFTs should be carried out.

Performance improvement in polymeric thin film transistors using chemically modified both silver bottom contacts and dielectric surfaces

An efficient interface modification is introduced to improve the performance of polymeric thin film transistors. This efficient interface modification is first achieved by 4-fluorothiophenol（4-FTP） self-assembled monolayers（SAM） to chemically treat the silver source–drain（S/D） contacts while the silicon oxide（SiO2） dielectric interface is further primed by either hexamethyldisilazane（HMDS） or octyltrichlorosilane（OTS-C8）. Results show that contact resistance is the dominant factor that limits the field effect mobility of the PTDPPTFT4 transistors. With proper surface modification applied to both the dielectric surface and the bottom contacts, the field effect mobilities of the bottom-gate bottom-contact PTDPPTFT4 transistors were significantly improved from 0.15 cm^2·V^-1·s^-1 to 0.91 cm^2·V^-1·s^-1.

High-throughput fabrication and semi-automated characterization of oxide thin film transistors

High throughput experimental methods are known to accelerate the rate of research,development,and deployment of electronic materials.For example,thin films with lateral gradients in composition,thickness,or other parameters have been used alongside spatially-resolved characterization to assess how various physical factors affect the material properties under varying measurement conditions.Similarly,multi-layer electronic devices that contain such graded thin films as one or more of their layers can also be characterized spatially in order to optimize the performance.In this work,we apply these high throughput experimental methods to thin film transistors(TFTs),demonstrating combinatorial channel layer growth,device fabrication,and semi-automated characterization using sputtered oxide TFTs as a case study.We show that both extrinsic and intrinsic types of device gradients can be generated in a TFT library,such as channel thickness and length,channel cation compositions,and oxygen atmosphere during deposition.We also present a semi-automated method to measure the 44 devices fabricated on a 50 mm×50 mm substrate that can help to identify properly functioning TFTs in the library and finish the measurement in a short time.Finally,we propose a fully automated characterization system for similar TFT libraries,which can be coupled with high throughput data analysis.These results demonstrate that high throughput methods can accelerate the investigation of TFTs and other electronic devices.

Temperature Dependence of Electrical Characteristics in Indium-Zinc-Oxide Thin Film Transistors from 10 K to 400 K

The transfer characteristics of amorphous indium-zinc-oxide thin film transistors are measured in the temperature range of 10-400K. The variation of electrical parameters （threshold voltage, field effect mobility, sub-threshold swing, and leafage current） with decreasing temperature are then extracted and analyzed. Moreover, the dom- inated carrier transport mechanisms at different temperature regions are investigated. The experimental data show that the carrier transport mechanism may change from trap-limited conduction to variable range hopping conduction at lower temperature. Moreover, the field effect mobilities are also extracted and simulated at various temperatures.

Contact-Size-Dependent Cutoff Frequency of Bottom-Contact Organic Thin Film Transistors

The contact-size-dependent characteristic of cutoff frequency fT in bottom-contact organic thin film transistors （OTFTs） is studied. The effects of electrode thickness, field-effect mobility, channel length and gate-source voltage on the contact length （source and drain electrodes＇ length） related contact resistance of bottom-contact OTFTs are performed with a modified transmission line model. It is found that the contact resistance increases dramatically when the contact length is scaled down to 20O nm. With the help of the contact length related contact resistance, contact-size-dependent fT Of bottom-contact OTFTs is studied and it is found that fr increases with the decrease of the contact length in bottom-contact OTFTs.

Total Ionizing Dose Radiation Effects in the P-Type Polycrystalline Silicon Thin Film Transistors

The total ionizing dose radiation effects in the polycrystalline silicon thin film transistors are studied. Transfer characteristics, high-frequency capacitance-voltage curves and low-frequency noises (LFN) are measured before and after radiation. The experimental results show that threshold voltage and hole-field-effect mobility decrease, while sub-threshold swing and low-frequency noise increase with the increase of the total dose. The contributions of radiation induced interface states and oxide trapped charges to the shift of threshold voltage are also estimated. Furthermore, spatial distributions of oxide trapped charges before and after radiation are extracted based on the LFN measurements.

Low-Frequency Noise in Amorphous Indium Zinc Oxide Thin Film Transistors with Aluminum Oxide Gate Insulator

Low-frequency noise（LFN） in all operation regions of amorphous indium zinc oxide（a-IZO） thin film transistors（TFTs） with an aluminum oxide gate insulator is investigated. Based on the LFN measured results, we extract the distribution of localized states in the band gap and the spatial distribution of border traps in the gate dielectric,and study the dependence of measured noise on the characteristic temperature of localized states for a-IZO TFTs with Al2 O3 gate dielectric. Further study on the LFN measured results shows that the gate voltage dependent noise data closely obey the mobility fluctuation model, and the average Hooge＇s parameter is about 1.18×10^-3.Considering the relationship between the free carrier number and the field effect mobility, we simulate the LFN using the △N-△μ model, and the total trap density near the IZO/oxide interface is about 1.23×10^18 cm^-3eV^-1.

Influence of Temperature and Pentacene Thickness on the Electrical Parameters in Top Gate Organic Thin Film Transistor

In this contribution, we report on the effect of pentacene thickness and temperature on the performance of top gate transistors. We first investigated the temperature dependence of the transport properties in the temperature range of 258 K - 353 K. The electrical characteristics showed that the threshold voltage (VT) and the onset voltage (Von) remain unchanged. However, the subthreshold current (Ioff), the on-current (Ion) and the field effect mobility (μ) are highly affected with a slight deterioration of subthreshold slope. We observed Arrhenius-like behavior suggesting a thermally activated mobility with an activation energy EA = 68 meV. Moreover the dependence of the charge carrier mobility on the organic semiconductor thickness has also been studied. The mobility decreased as the pentacene thickness increases whereas the threshold voltage and Ioff current remain minimally affected. In order to understand the transport properties and in view to put in light morphology peculiarities of pentacene, AFM images were performed. It turns out that the pentacene grain sizes are smaller and disorganized as the film thickness increases, and charge carriers are more prone to be trapped, leading to decrease the field effect mobility and the Ion current. The devices were also tested under bias stress and the transistors with low thicknesses exhibited a relatively good electrical stability compared to those with high pentacene thicknesses. This work points out the influence of temperature, semiconductor thickness and bias stress effect on the device performance and stability of transistor using top gate configuration.

Temperature Dependence of Electrical Properties of Organic Thin Film Transistors Based on pn Heterojuction and Their Applications in Temperature Sensors

Organic thin film transistors based on an F16CuPc/α6T pn heterojunction have been fabricated and analyzed to investigate the temperature dependence of electrical properties and apply in temperature sensors. The mobility follows a thermally activated hopping process. At temperatures over 200 K, the value of thermal activation energy (EA) is 40. 1 meV, similar to that of the single-layer device. At temperatures ranging from 100 to 200 K, we have a second regime with a much lower EA of 16.3 meV, where the charge transport is dominated by shallow traps. Similarly, at temperatures above 200 K, threshold voltage (VT) increases linearly with decreasing temperature, and the variations of VT of 0.185 V/K is larger than the variation of VT (~0.020 V/K) in the single layer devices. This result is due to the interface dipolar charges. At temperatures ranging from 100 K to 200 K, we have a second regime with much lower variations of 0.090 V/K. By studying gate voltage (VG)-dependence temperature variation factor (k), the maximum value of k (~0.11 dec/K) could be obtained at VG = 5 V. Furthermore, the pn heterojunction device could be characterized as a temperature sensor well working at low operating voltages.

Investigation and active suppression of self-heating induced degradation in amorphous InGaZnO thin film transistors

Self-heating effect in amorphous InGaZnO thin-film transistors remains a critical issue that degrades device performance and stability, hindering their wider applications. In this work, pulsed current–voltage analysis has been applied to explore the physics origin of self-heating induced degradation, where Joule heat is shortly accumulated by drain current and dissipated in repeated time cycles as a function of gate bias. Enhanced positive threshold voltage shift is observed at reduced heat dissipation time, higher drain current, and increased gate width. A physical picture of Joule heating assisted charge trapping process has been proposed and then verified with pulsed negative gate bias stressing scheme, which could evidently counteract the self-heating effect through the electric-field assisted detrapping process. As a result, this pulsed gate bias scheme with negative quiescent voltage could be used as a possible way to actively suppress self-heating related device degradation.