Fabrication of Bottom-Gate and Top-Gate Transparent ZnO Thin Film Transistors

Transparent zinc oxide thin film transistors （ZnO-TFTs） with bottom-gate and top-gate structures were constructed on 50mm silica glass substrates. The ZnO films were deposited by RF magnetron sputtering and SiO2 films served as the gate insulator layer. We found that the ZnO-TFTs with bottom-gate structure have better electrical performance than those with top-gate structure. The bottom-gate ZnO-TFTs operate as an n-channel enhancement mode, which have clear pinch off and saturation characteristics. The field effect mobility, threshold voltage, and the current on/off ratio were determined to be 18.4cm^2/（V ·s）, - 0. 5V and 10^4 , respectively. Meanwhile, the top-gate ZnO-TFTs exhibit n-chan- nel depletion mode operation and no saturation characteristics were detected. The electrical difference of the devices may be due to the different character of the interface between the channel and insulator layers. The two transistors types have high transparency in the visible light region.

Influence of High Temperature Treatment on the Performance of Nickel-Induced Laterally Crystallized Thin Film Transistors

Well known for their good performance,thin film transistors (TFTs) with active layers which were nickel induced laterally crystallized,are fabricated by conventional process of dual gate CMOS.The influence of pre high temperature treatment of device fabrication on the performance of TFTs is also investigated.The experiment shows that the high temperature treatment affects the performance of the devices strongly.The best performance is obtained by adopting pre treatment of 1000℃.The mobility of 314cm 2/(V·s) is obtained at NMOS TFTs with pre treatment of 1000℃,which is 10% and 22% higher than that treated at 1100℃ and without pre high temperature treatment,respectively.A maximum on/off current ratio of 3×10 8 is also obtained at 1000℃.Further investigation of uniformity verifies that the result is reliable.

Atomic layer deposition for nanoscale oxide semiconductor thin film transistors:review and outlook

Since the first report of amorphous In–Ga–Zn–O based thin film transistors,interest in oxide semiconductors has grown.They offer high mobility,low off-current,low process temperature,and wide flexibility for compositions and processes.Unfortunately,depositing oxide semiconductors using conventional processes like physical vapor deposition leads to problematic issues,especially for high-resolution displays and highly integrated memory devices.Conventional approaches have limited process flexibility and poor conformality on structured surfaces.Atomic layer deposition(ALD)is an advanced technique which can provide conformal,thickness-controlled,and high-quality thin film deposition.Accordingly,studies on ALD based oxide semiconductors have dramatically increased recently.Even so,the relationships between the film properties of ALD-oxide semiconductors and the main variables associated with deposition are still poorly understood,as are many issues related to applications.In this review,to introduce ALD-oxide semiconductors,we provide:(a)a brief summary of the history and importance of ALD-based oxide semiconductors in industry,(b)a discussion of the benefits of ALD for oxide semiconductor deposition(in-situ composition control in vertical distribution/vertical structure engineering/chemical reaction and film properties/insulator and interface engineering),and(c)an explanation of the challenging issues of scaling oxide semiconductors and ALD for industrial applications.This review provides valuable perspectives for researchers who have interest in semiconductor materials and electronic device applications,and the reasons ALD is important to applications of oxide semiconductors.

Effects of active layer thickness on performance and stability of dual-active-layer amorphous InGaZnO thin-film transistors

Dual-active-layer(DAL)amorphous InGaZnO(IGZO)thin-film transistors(TFTs)are fabricated at low temperature without post-annealing.A bottom low-resistance(low-R)IGZO layer and a top high-resistance(high-R)IGZO layer constitute the DAL homojunction with smooth and high-quality interface by in situ modulation of oxygen composition.The performance of the DAL TFT is significantly improved when compared to that of a single-active-layer TFT.A detailed investigation was carried out regarding the effects of the thickness of both layers on the electrical properties and gate bias stress stabilities.It is found that the low-R layer improves the mobility,ON/OFF ratio,threshold voltage and hysteresis voltage by passivating the defects and providing a smooth interface.The high-R IGZO layer has a great impact on the hysteresis,which changes from clockwise to counterclockwise.The best TFT shows a mobility of 5.41 cm^2/V·s,a subthreshold swing of 95.0 mV/dec,an ON/OFF ratio of 6.70×10^7,a threshold voltage of 0.24 V,and a hysteresis voltage of 0.13 V.The value of threshold voltage shifts under positive gate bias stress decreases when increasing the thickness of both layers.

High-photosensitivity polymer thin-film transistors based on poly(3-hexylthiophene)

Polymer thin-film transistors （PTFTs） based on poly（3-hexylthiophene） are fabricated by the spin-coating process, and their photo-sensing characteristics are investigated under steady-state visible-light illumination. The photosensitivity of the device is strongly modulated by gate voltage under various illuminations. When the device is in the subthreshold operating mode, a significant increase in its drain current is observed with a maximum photosensitivity of 1.7×10^3 at an illumination intensity of 1200 lx, and even with a relatively high photosensitivity of 611 at a low illumination intensity of 100 lx. However, when the device is in the on-state operating mode, the photosensitivity is very low： only 1.88 at an illumination intensity of 1200 lx for a gate voltage of -20 V and a drain voltage of -20 V. The results indicate that the devices could be used as photo-detectors or sensors in the range of visible light. The modulation mechanism of the photosensitivity in the PTFT is discussed in detail.

Self-assembled monolayers enhance the performance of oxide thin-film transistors

Thin-film transistors(TFTs)based on oxide semiconductors have gained a lot of attention in applications such as displays and sensors particularly in recent years due to the advantages of oxide semiconductors like high mobility,good uniformity over large area and low deposition temperature[1−4].However,the defects/traps at dielectric/channel interface and top surface of oxide TFTs might dramatically degrade device performance including current on/off ratio,mobility and most importantly stability[5,6],making it quite urgent to systematically make effective interface engineering to improve TFT performance.

Concise Modeling of Amorphous Dual-Gate In-Ga-Zn-O Thin-Film Transistors for Integrated Circuit Designs

An analytical model for current-voltage behavior of amorphous In-Ga-Zn-O thin-film transistors（a-IGZO TFTs）with dual-gate structures is developed.The unified expressions for synchronous and asynchronous operating modes are derived on the basis of channel charges,which are controlled by gate voltage.It is proven that the threshold voltage of asynchronous dual-gate IGZO TFTs is adjusted in proportion to the ratio of top insulating capacitance to the bottom insulating capacitance（C_（TI）/C_（BI））.Incorporating the proposed model with Verilog-A,a touch-sensing circuit using dual-gate structure is investigated by SPICE simulations.Comparison shows that the touch sensitivity is increased by the dual-gate IGZO TFT structure.

Carrier Transport Across Grain Boundaries in Polycrystalline Silicon Thin Film Transistors

We established a model for investigating polycrystalline silicon（poly-Si） thin film transistors（TFTs）.The effect of grain boundaries（GBs） on the transfer characteristics of TFT was analyzed by considering the number and the width of grain boundaries in the channel region,and the dominant transport mechanism of carrier across grain boundaries was subsequently determined.It is shown that the thermionic emission（TE） is dominant in the subthreshold operating region of TFT regardless of the number and the width of grain boundary.To a poly-Si TFT model with a 1 nm-width grain boundary,in the linear region,thermionic emission is similar to that of tunneling（TU）,however,with increasing grain boundary width and number,tunneling becomes dominant.

High-throughput fabrication and semi-automated characterization of oxide thin film transistors

High throughput experimental methods are known to accelerate the rate of research,development,and deployment of electronic materials.For example,thin films with lateral gradients in composition,thickness,or other parameters have been used alongside spatially-resolved characterization to assess how various physical factors affect the material properties under varying measurement conditions.Similarly,multi-layer electronic devices that contain such graded thin films as one or more of their layers can also be characterized spatially in order to optimize the performance.In this work,we apply these high throughput experimental methods to thin film transistors(TFTs),demonstrating combinatorial channel layer growth,device fabrication,and semi-automated characterization using sputtered oxide TFTs as a case study.We show that both extrinsic and intrinsic types of device gradients can be generated in a TFT library,such as channel thickness and length,channel cation compositions,and oxygen atmosphere during deposition.We also present a semi-automated method to measure the 44 devices fabricated on a 50 mm×50 mm substrate that can help to identify properly functioning TFTs in the library and finish the measurement in a short time.Finally,we propose a fully automated characterization system for similar TFT libraries,which can be coupled with high throughput data analysis.These results demonstrate that high throughput methods can accelerate the investigation of TFTs and other electronic devices.

Temperature-dependent bias-stress-induced electrical instability of amorphous indium-gallium-zinc-oxide thin-film transistors

The time and temperature dependence of threshold voltage shift under positive-bias stress（PBS） and the following recovery process are investigated in amorphous indium-gallium-zinc-oxide（a-IGZO） thin-film transistors. It is found that the time dependence of threshold voltage shift can be well described by a stretched exponential equation in which the time constant τ is found to be temperature dependent. Based on Arrhenius plots, an average effective energy barrier Eτ stress= 0.72 eV for the PBS process and an average effective energy barrier Eτ recovery= 0.58 eV for the recovery process are extracted respectively. A charge trapping/detrapping model is used to explain the threshold voltage shift in both the PBS and the recovery process. The influence of gate bias stress on transistor performance is one of the most critical issues for practical device development.

Negative gate bias stress effects on conduction and low frequency noise characteristics in p-type poly-Si thin-film transistors

The instability of p-channel low-temperature polycrystalline silicon thin film transistors(poly-Si TFTs)is investigated under negative gate bias stress(NBS)in this work.Firstly,a series of negative bias stress experiments is performed,the significant degradation behaviors in current-voltage characteristics are observed.As the stress voltage decreases from-25 V to-37 V,the threshold voltage and the sub-threshold swing each show a continuous shift,which is induced by gate oxide trapped charges or interface state.Furthermore,low frequency noise(LFN)values in poly-Si TFTs are measured before and after negative bias stress.The flat-band voltage spectral density is extracted,and the trap concentration located near the Si/SiO2 interface is also calculated.Finally,the degradation mechanism is discussed based on the current-voltage and LFN results in poly-Si TFTs under NBS,finding out that Si-OH bonds may be broken and form Si*and negative charge OH-under negative bias stress,which is demonstrated by the proposed negative charge generation model.

Modeling of polycrystalline ZnO thin-film transistors with a consideration of the deep and tail states

We report a model of the carrier transport and the subgap density of states in a polycrystalline ZnO film for simulating a polycrystalline ZnO thin film transistor. This simple model considering the deep and the band tail states reproduces well the characteristics of polycrystalline ZnO thin film transistors. Furthermore, using the developed model, we study the effects of defect parameters on the electrical performances of the polycrystalline ZnO thin film transistors.

The influence of SiNx substrate on crystallinity of μc-Si film used in thin film transistors

This paper found that the crystalline volume ratio （Xc） of μc-Si deposited on SiNx substrate is higher than that on 7059 glass. At the same silane concentration （SC） （for example, at SC=2%）, the Xc of μc-Si deposited on SiNx is more than 64%, but just 44% if deposited on Conning 7059. It considered that the ‘hills＇ on SiNx substrate would promote the crystalline growth of μc-Si thin film, which has been confirmed by atomic force microscope （AFM） observation. Comparing several thin film transistor （TFT） samples whose active-layer were deposited under various SC, this paper found that the appropriate SC for the μc-Si thin film used in TFT as active layer should be more than 2%, and Xc should be around 50%. Additionally, the stability comparison of μc-Si TFT and a-Si TFT is shown in this paper.

Degradation of current–voltage and low frequency noise characteristics under negative bias illumination stress in InZnO thin film transistors

The instabilities of indium–zinc oxide thin film transistors under bias and/or illumination stress are studied in this paper. Firstly, illumination experiments are performed, which indicates the variations of current–voltage characteristics and electrical parameters（such as threshold voltage and sub-threshold swing） are dominated by the stress-induced ionized oxygen vacancies and acceptor-like states. The dependence of degradation on light wavelength is also investigated. More negative shift of threshold voltage and greater sub-threshold swing are observed with the decrease of light wavelength.Subsequently, a negative bias illumination stress experiment is carried out. The degradation of the device is aggravated due to the decrease of recombination effects between ionized oxygen vacancies and free carriers. Moreover, the contributions of ionized oxygen vacancies and acceptor-like states are separated by using the mid-gap method. In addition, ionized oxygen vacancies are partially recombined at room temperature and fully recombined at high temperature. Finally, low-frequency noise is measured before and after negative bias illumination stress. Experimental results show few variations of the oxide trapped charges are generated during stress, which is consistent with the proposed mechanism.

Positive gate bias stress-induced hump-effect in elevated-metal metal-oxide thin film transistors

Under the action of a positive gate bias stress, a hump in the subthreshold region of the transfer characteristic is observed for the amorphous indium-gallium-zinc oxide thin film transistor, which adopts an elevated-metal metal-oxide structure. As stress time goes by, both the on-state current and the hump shift towards the negative gate-voltage direction. The humps occur at almost the same current levels for devices with different channel widths, which is attributed to the parasitic transistors located at the channel width edges. Therefore, we propose that the positive charges trapped at the back-channel interface cause the negative shift, and the origin of the hump is considered as being due to more positive charges trapped at the edges along the channel width direction. On the other hand, the hump-effect becomes more significant in a short channel device （L=2 μm）. It is proposed that the diffusion of oxygen vacancies takes place from the high concentration source/drain region to the intrinsic channel region.

Performance improvement in pentacene organic thin film transistors by inserting a C_(60) ultrathin layer

The contact effect on the performances of organic thin film transistors is studied here. A C60 ultrathin layer is inserted between Al source-drain electrode and pentacene to reduce the contact resistance. By a 3 nm C60 modification, the injection barrier is lowered and the contact resistance is reduced. Thus, the field-effect mobility increases from 0.12 to 0.52 cm2/（V.s）. It means that inserting a C60 ultra thin layer is a good method to improve the organic thin film transistor （OTFT） performance. The output curve is simulated by using a charge drift model. Considering the contact effect, the field effect mobility is improved to 1.15 cm2/（V-s）. It indicates that further reducing the contact resistance of OTFTs should be carried out.

Weak avalanche multiplication in SiGe heterojunction bipolar transistors on thin film silicon-on-insulator

In this paper, we propose an analytical avalanche multiplication model for the next generation of SiGe silicon- on-insulator （SOI） heterojunction bipolar transistors （HBTs） and consider their vertical and lateral impact ionizations for the first time. Supported by experimental data, the analytical model predicts that the avalanche multiplication governed by impact ionization shows kinks and the impact ionization effect is small compared with that of the bulk HBT, resulting in a larger base-collector breakdown voltage. The model presented in the paper is significant and has useful applications in the design and simulation of the next generation of SiCe SOI BiCMOS technology.

Performance improvement in polymeric thin film transistors using chemically modified both silver bottom contacts and dielectric surfaces

An efficient interface modification is introduced to improve the performance of polymeric thin film transistors. This efficient interface modification is first achieved by 4-fluorothiophenol（4-FTP） self-assembled monolayers（SAM） to chemically treat the silver source–drain（S/D） contacts while the silicon oxide（SiO2） dielectric interface is further primed by either hexamethyldisilazane（HMDS） or octyltrichlorosilane（OTS-C8）. Results show that contact resistance is the dominant factor that limits the field effect mobility of the PTDPPTFT4 transistors. With proper surface modification applied to both the dielectric surface and the bottom contacts, the field effect mobilities of the bottom-gate bottom-contact PTDPPTFT4 transistors were significantly improved from 0.15 cm^2·V^-1·s^-1 to 0.91 cm^2·V^-1·s^-1.

Review of flexible and transparent thin-film transistors based on zinc oxide and related materials

Flexible and transparent electronics enters into a new era of electronic technologies.Ubiquitous applications involve wearable electronics,biosensors,flexible transparent displays,radio-frequency identifications（RFIDs）,etc.Zinc oxide（ZnO） and relevant materials are the most commonly used inorganic semiconductors in flexible and transparent devices,owing to their high electrical performances,together with low processing temperatures and good optical transparencies.In this paper,we review recent advances in flexible and transparent thin-film transistors（TFTs） based on ZnO and relevant materials.After a brief introduction,the main progress of the preparation of each component（substrate,electrodes,channel and dielectrics） is summarized and discussed.Then,the effect of mechanical bending on electrical performance is highlighted.Finally,we suggest the challenges and opportunities in future investigations.

Homojunction structure amorphous oxide thin film transistors with ultra-high mobility

Amorphous oxide semiconductors(AOS)have unique advantages in transparent and flexible thin film transistors(TFTs)applications,compared to low-temperature polycrystalline-Si(LTPS).However,intrinsic AOS TFTs are difficult to obtain field-effect mobility(μFE)higher than LTPS(100 cm^(2)/(V·s)).Here,we design ZnAlSnO(ZATO)homojunction structure TFTs to obtainμFE=113.8 cm^(2)/(V·s).The device demonstrates optimized comprehensive electrical properties with an off-current of about1.5×10^(-11)A,a threshold voltage of–1.71 V,and a subthreshold swing of 0.372 V/dec.There are two kinds of gradient coupled in the homojunction active layer,which are micro-crystallization and carrier suppressor concentration gradient distribution so that the device can reduce off-current and shift the threshold voltage positively while maintaining high field-effect mobility.Our research in the homojunction active layer points to a promising direction for obtaining excellent-performance AOS TFTs.