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Breakdown voltage model and structure realization of a thin silicon layer with linear variable doping on a silicon on insulator high voltage device with multiple step field plates 被引量:2
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作者 乔明 庄翔 +4 位作者 吴丽娟 章文通 温恒娟 张波 李肇基 《Chinese Physics B》 SCIE EI CAS CSCD 2012年第10期504-511,共8页
Based on the theoretical and experimental investigation of a thin silicon layer(TSL) with linear variable doping(LVD) and further research on the TSL LVD with a multiple step field plate(MSFP),a breakdown voltag... Based on the theoretical and experimental investigation of a thin silicon layer(TSL) with linear variable doping(LVD) and further research on the TSL LVD with a multiple step field plate(MSFP),a breakdown voltage(BV) model is proposed and experimentally verified in this paper.With the two-dimensional Poisson equation of the silicon on insulator(SOI) device,the lateral electric field in drift region of the thin silicon layer is assumed to be constant.For the SOI device with LVD in the thin silicon layer,the dependence of the BV on impurity concentration under the drain is investigated by an enhanced dielectric layer field(ENDIF),from which the reduced surface field(RESURF) condition is deduced.The drain in the centre of the device has a good self-isolation effect,but the problem of the high voltage interconnection(HVI) line will become serious.The two step field plates including the source field plate and gate field plate can be adopted to shield the HVI adverse effect on the device.Based on this model,the TSL LVD SOI n-channel lateral double-diffused MOSFET(nLDMOS) with MSFP is realized.The experimental breakdown voltage(BV) and specific on-resistance(R on,sp) of the TSL LVD SOI device are 694 V and 21.3 ·mm 2 with a drift region length of 60 μm,buried oxide layer of 3 μm,and silicon layer of 0.15 μm,respectively. 展开更多
关键词 breakdown voltage model enhanced dielectric layer field thin silicon layer linear variable doping multiple step field plates
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Large energy-loss straggling of swift heavy ions in ultra-thin active silicon layers 被引量:2
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作者 张战刚 刘杰 +13 位作者 侯明东 孙友梅 赵发展 刘刚 韩郑生 耿超 刘建德 习凯 段敬来 姚会军 莫丹 罗捷 古松 刘天奇 《Chinese Physics B》 SCIE EI CAS CSCD 2013年第9期505-511,共7页
Monte Carlo simulations reveal considerable straggling of energy loss by the same ions with the same energy in fully-depleted silicon-on-insulator (FDSOI) devices with ultra-thin sensitive silicon layers down to 2.5... Monte Carlo simulations reveal considerable straggling of energy loss by the same ions with the same energy in fully-depleted silicon-on-insulator (FDSOI) devices with ultra-thin sensitive silicon layers down to 2.5 rim. The absolute straggling of deposited energy decreases with decreasing thickness of the active silicon layer. While the relative straggling increases gradually with decreasing thickness of silicon films and exhibits a sharp rise as the thickness of the silicon film descends below a threshold value of 50 nm, with the dispersion of deposited energy ascending above ~10%. Ion species and energy dependence of the energy-loss straggling are also investigated. For a given beam, the dispersion of deposited energy results in large uncertainty on the actual linear energy transfer (LET) of incident ions, and thus single event effect (SEE) responses, which pose great challenges for traditional error rate prediction methods. 展开更多
关键词 single event effects energy-loss straggling ultra-thin silicon layer Monte Carlo simulation
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Effect of emitter layer doping concentration on the performance of a silicon thin film heterojunction solar cell
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作者 张磊 沈鸿烈 +3 位作者 岳之浩 江丰 吴天如 潘园园 《Chinese Physics B》 SCIE EI CAS CSCD 2013年第1期457-461,共5页
A novel type of n/i/i/p heterojunction solar cell with a-Si:H(15 nm)/a-Si:H(10 nm)/epitaxial c-Si(47 p.m)/epitaxial c-Si(3 um) structure is fabricated by using the layer transfer technique, and the emitter l... A novel type of n/i/i/p heterojunction solar cell with a-Si:H(15 nm)/a-Si:H(10 nm)/epitaxial c-Si(47 p.m)/epitaxial c-Si(3 um) structure is fabricated by using the layer transfer technique, and the emitter layer is deposited by hot wire chemical vapour deposition. The effect of the doping concentration of the emitter layer Sd (Sd=PH3/(PH3 +SiH4+H2)) on the performance of the solar cell is studied by means of current density-voltage and external quantum efficiency. The results show that the conversion efficiency of the solar cell first increases to a maximum value and then decreases with Sd increasing from 0.1% to 0.4%. The best performance of the solar cell is obtained at Sd = 0.2% with an open circuit voltage of 534 mV, a short circuit current density of 23.35 mA/cm2, a fill factor of 63.3%, and a conversion efficiency of 7.9%. 展开更多
关键词 layer transfer silicon thin film heterojunction solar cell hot wire chemical vapor deposition doping concentration
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Improvement in the electrical performance and bias-stress stability of dual-active-layered silicon zinc oxide/zinc oxide thin-film transistor
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作者 刘玉荣 赵高位 +1 位作者 黎沛涛 姚若河 《Chinese Physics B》 SCIE EI CAS CSCD 2016年第8期452-457,共6页
Si-doped zinc oxide(SZO) thin films are deposited by using a co-sputtering method,and used as the channel active layers of ZnO-based TFTs with single and dual active layer structures.The effects of silicon content o... Si-doped zinc oxide(SZO) thin films are deposited by using a co-sputtering method,and used as the channel active layers of ZnO-based TFTs with single and dual active layer structures.The effects of silicon content on the optical transmittance of the SZO thin film and electrical properties of the SZO TFT are investigated.Moreover,the electrical performances and bias-stress stabilities of the single- and dual-active-layer TFTs are investigated and compared to reveal the effects of the Si doping and dual-active-layer structure.The average transmittances of all the SZO films are about 90% in the visible light region of 400 nm-800 nm,and the optical band gap of the SZO film gradually increases with increasing Si content.The Si-doping can effectively suppress the grain growth of ZnO,revealed by atomic force microscope analysis.Compared with that of the undoped ZnO TFT,the off-state current of the SZO TFT is reduced by more than two orders of magnitude and it is 1.5 × 10^-12 A,and thus the on/off current ratio is increased by more than two orders of magnitude.In summary,the SZO/ZnO TFT with dual-active-layer structure exhibits a high on/off current ratio of 4.0 × 10^6 and superior stability under gate-bias and drain-bias stress. 展开更多
关键词 thin film transistor (TFT) silicon-doped zinc oxide dual-active-layer structure bias-stress stability
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A new analytical model of high voltage silicon on insulator(SOI) thin film devices 被引量:5
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作者 胡盛东 张波 李肇基 《Chinese Physics B》 SCIE EI CAS CSCD 2009年第1期315-319,共5页
A new analytical model of high voltage silicon on insulator (SOI) thin film devices is proposed, and a formula of silicon critical electric field is derived as a function of silicon film thickness by solving a 2D Po... A new analytical model of high voltage silicon on insulator (SOI) thin film devices is proposed, and a formula of silicon critical electric field is derived as a function of silicon film thickness by solving a 2D Poisson equation from an effective ionization rate, with a threshold energy taken into account for electron multiplying. Unlike a conventional silicon critical electric field that is constant and independent of silicon film thickness, the proposed silicon critical electric field increases sharply with silicon fihn thickness decreasing especially in the case of thin films, and can come to 141V/μm at a film thickness of 0.1 μm which is much larger than the normal value of about 30 V/μm. From the proposed formula of silicon critical electric field, the expressions of dielectric layer electric field and vertical breakdown voltage (VB,V) are obtained. Based on the model, an ultra thin film can be used to enhance dielectric layer electric field and so increase vertical breakdown voltage for SOI devices because of its high silicon critical electric field, and with a dielectric layer thickness of 2 μm the vertical breakdown voltages reach 852 and 300V for the silicon film thicknesses of 0.1 and 5μm, respectively. In addition, a relation between dielectric layer thickness and silicon film thickness is obtained, indicating a minimum vertical breakdown voltage that should be avoided when an SOI device is designed. 2D simulated results and some experimental results are in good agreement with analytical results. 展开更多
关键词 silicon critical electric field breakdown voltage thin silicon layer SOI high voltage device
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The study of amorphous incubation layers during the growth of microcrystalline silicon films under different deposition conditions 被引量:1
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作者 陈永生 徐艳华 +3 位作者 谷锦华 卢景霄 杨仕娥 郜小勇 《Chinese Physics B》 SCIE EI CAS CSCD 2010年第8期567-571,共5页
The structural un-uniformity of microcrystalline silicon, thin film, amorphous incubation layerc-Si:H films prepared using very high frequency plasma-enhanced chemical vapour deposition method has been investigated ... The structural un-uniformity of microcrystalline silicon, thin film, amorphous incubation layerc-Si:H films prepared using very high frequency plasma-enhanced chemical vapour deposition method has been investigated by Raman spectroscopy, spectroscopic ellipsometer and atomic force mi- croscopy. It was found that the formation of amorphous incubation layer was caused by the back diffusion of SiH4 and the amorphous induction of glass surface during the initial ignition process, and growth of the incubation layer can be suppressed and uniform μc-Si:H phase is generated by the application of delayed initial SiH4 density and silane profiling methods. 展开更多
关键词 microcrystalline silicon thin film amorphous incubation layer
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Fabrication and Characterization of PZN-4.5PT Inorganic Perovskites Nanoparticles Thin Films Deposited on P-Type Silicon Substrate
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作者 Rémi Ndioukane Moussa Touré +3 位作者 Diouma Kobor Laurence Motte Marcel Pasquinelli Jeanne Solard 《Journal of Modern Physics》 2018年第2期259-272,共14页
This work involves an investigation of nanostructures, microelectronic properties and domain engineering of nanoparticles thin layers of Pb(Zn1/ 3Nb2/3)O3-PbTiO3 (PZN-PT) ferroelectric single crystals deposited on nan... This work involves an investigation of nanostructures, microelectronic properties and domain engineering of nanoparticles thin layers of Pb(Zn1/ 3Nb2/3)O3-PbTiO3 (PZN-PT) ferroelectric single crystals deposited on nanostructured silicon substrate. In this study, devices made from PZN-4.5PT nanoparticles thin films successfully deposited on silicon substrate have been studied and discussed. SEM images show the formation of local black circles and hexagonal shapes probably due to the nucleation of a new Si-gel component or phase induced by annealing. Micro Xray Fluorescence mapping shows that the high values of Si and B atoms (&cong;7 and 4 normalized unit respectively) can be explained by the fact that the substrate is p-type silicon. The most interesting result of optical measurements is the very good absorption for all the thin films in UV, Visible and NIR regions with values from 70% to 90% in UV, from 75% to 93% in Visible and NIR. Tauc plots present particularities (rarely encountered behavior) with different segments or absorption changes showing the presence of multiple band gaps coming from the heterogeneity of the thin films (nanowires, gel and nanoparticles). Their values are 1.9 and 2.8 eV for DKRN-Gel, 2.1 and 3.1 eV for DKRN-UD and 2.1 and 3.2 eV for DKRN-D) corresponding respectively to the band gap of nanowires and that of the gel while the last ones correspond to the undoped and doped nanoparticles (3.1 and 3.2 eV respectively). 展开更多
关键词 NANOSTRUCTURES PEROVSKITE NANOPARTICLES silicon thin layer Band Gap
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Characteristics of Si^+/B^+ dual implanted silicon wafers
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作者 周继承 黄伯云 《中国有色金属学会会刊:英文版》 CSCD 2001年第5期753-755,共3页
Thin p + layers with good electrical properties were fabricated by RTA (rapid thermal annealing) with post FA (furance annealing) of Si +/B + dual implanted silicon wafers. The electrical and structural characteristic... Thin p + layers with good electrical properties were fabricated by RTA (rapid thermal annealing) with post FA (furance annealing) of Si +/B + dual implanted silicon wafers. The electrical and structural characteristics of thin p + layers have been measured by FPP (four point probe), SRP (spreading resistance probe), RBS/channelling. Optimizing the implantation and annealing processes, especially using the thermal cycle of RTA followed by FA, shallow p +n junctions can be fabricated, which shows excellent I V characteristics with revers bias leakage current densities of 1.8?nA/cm 2 at -1.4?V. 展开更多
关键词 rapid thermal annealing dual ion implantation silicon thin p + layers
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薄规格无取向硅钢的卷取错层原因与控制 被引量:1
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作者 温如军 刘荆磊 +3 位作者 侯沛江 陈祥 张立文 王朕 《山西冶金》 CAS 2024年第4期224-226,共3页
薄规格无取向硅钢的卷取错层严重影响产品的出厂质量,如何将错层控制在±1 mm以内是生产现场的重要研究课题。于是从薄规格无取向硅钢现有生产设备和工艺技术入手,从剪切不齐和卷取不齐两个方面探索错层产生的原因,总结控制措施并... 薄规格无取向硅钢的卷取错层严重影响产品的出厂质量,如何将错层控制在±1 mm以内是生产现场的重要研究课题。于是从薄规格无取向硅钢现有生产设备和工艺技术入手,从剪切不齐和卷取不齐两个方面探索错层产生的原因,总结控制措施并在生产现场实施验证。 展开更多
关键词 无取向硅钢 薄规格 错层
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基于两步刻蚀工艺的锥形TSV制备方法
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作者 田苗 刘民 +3 位作者 林子涵 付学成 程秀兰 吴林晟 《半导体技术》 CAS 北大核心 2024年第4期316-322,共7页
以硅通孔(TSV)为核心的2.5D/3D封装技术可以实现芯片之间的高速、低功耗和高带宽的信号传输。常见的垂直TSV的制造工艺复杂,容易造成填充缺陷。锥形TSV的侧壁倾斜,开口较大,有利于膜层沉积和铜电镀填充,可降低工艺难度和提高填充质量。... 以硅通孔(TSV)为核心的2.5D/3D封装技术可以实现芯片之间的高速、低功耗和高带宽的信号传输。常见的垂直TSV的制造工艺复杂,容易造成填充缺陷。锥形TSV的侧壁倾斜,开口较大,有利于膜层沉积和铜电镀填充,可降低工艺难度和提高填充质量。在相对易于实现的刻蚀条件下制备了锥形TSV,并通过增加第二步刻蚀来改善锥形TSV形貌。成功制备了直径为10~40μm、孔口为喇叭形的锥形TSV。通过溅射膜层和铜电镀填充,成功实现了直径为15μm、深度为60μm的锥形TSV的连续膜层沉积和完全填充,验证了两步刻蚀工艺的可行性和锥形TSV在提高膜层质量和填充效果方面的优势。为未来高密度封装领域提供了一种新的TSV制备工艺,在降低成本的同时提高了2.5D/3D封装技术的性能。 展开更多
关键词 硅通孔(TSV) 锥形 种子层 电镀填充 薄膜沉积
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Si(111)邻位面衬底上InSb薄膜的外延生长及其可见光电导特性
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作者 杜绍增 方晨旭 +1 位作者 刘婷 李含冬 《半导体光电》 CAS 北大核心 2024年第5期811-816,共6页
锑化铟(InSb)因其在红外探测、高速电子学和量子计算等领域的卓越性能备受关注。文章探索了Si(111)邻位面衬底上InSb薄膜的异质外延生长,并研究了其光电导特性。尝试采用Bi缓冲层结合InSb两步法生长策略解决Si与InSb晶格失配和热膨胀系... 锑化铟(InSb)因其在红外探测、高速电子学和量子计算等领域的卓越性能备受关注。文章探索了Si(111)邻位面衬底上InSb薄膜的异质外延生长,并研究了其光电导特性。尝试采用Bi缓冲层结合InSb两步法生长策略解决Si与InSb晶格失配和热膨胀系数差异大的问题,在平坦Si(111)衬底上获得了高质量InSb(111)单晶薄膜。然而,在具有高密度台阶结构特征的Si(111)斜切衬底表面上生长得到的Bi(001)缓冲层存在大量倒反畴缺陷,在该表面上进一步生长得到的InSb薄膜均为多晶结构。所制备的InSb/Bi/Si异质结构在模拟日光辐照条件下显示出负光电导效应,应与异质结构界面态对InSb层光生载流子的捕获效应有关。 展开更多
关键词 INSB薄膜 SI衬底 临位面外延 Bi缓冲层
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薄有源层非晶硅薄膜晶体管特性的研究 被引量:5
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作者 张少强 徐重阳 +4 位作者 邹雪城 赵伯芳 周雪梅 王长安 戴永兵 《电子学报》 EI CAS CSCD 北大核心 1997年第2期53-56,共4页
本文研究了薄a-Si:H有源层结构的a-Si:HTFT的特性,实验结果表明,当a-Si:H层的厚度小于一个临界值时,a-Si:H厚度的变化对a-Si:HTFT静态特性的影响明显增大.文中详细分析了有源层背面空间电荷层... 本文研究了薄a-Si:H有源层结构的a-Si:HTFT的特性,实验结果表明,当a-Si:H层的厚度小于一个临界值时,a-Si:H厚度的变化对a-Si:HTFT静态特性的影响明显增大.文中详细分析了有源层背面空间电荷层对a-Si:HTFT特性的影响,从表面有效空间电荷层的概念出发,从理论上分析了有源层厚度与阈值电压的关系,计算的临界有源层厚度为130nm,这与实验结果基本一致. 展开更多
关键词 非晶硅 薄膜晶体管 有源层厚度 空间电行层
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硅片背面减薄技术研究 被引量:8
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作者 江海波 熊玲 +2 位作者 朱梦楠 邓刚 王小强 《半导体光电》 CAS 北大核心 2015年第6期930-932,963,共4页
硅片背面磨削减薄工艺中,机械磨削使硅片背面产生损伤,导致表面粗糙,且发生翘曲变形。分别采用粗磨、精磨、精磨后抛光和精磨后湿法腐蚀等四种不同背面减薄方法对15.24cm(6英寸)硅片进行了背面减薄,采用扫描电子显微镜对减薄后的硅片表... 硅片背面磨削减薄工艺中,机械磨削使硅片背面产生损伤,导致表面粗糙,且发生翘曲变形。分别采用粗磨、精磨、精磨后抛光和精磨后湿法腐蚀等四种不同背面减薄方法对15.24cm(6英寸)硅片进行了背面减薄,采用扫描电子显微镜对减薄后的硅片表面和截面形貌进行了表征,用原子力显微镜测试了硅片表面的粗糙度,用翘曲度测试仪测试了硅片的翘曲度。结果表明,经过粗磨与精磨后的硅片存在机械损伤,表面粗糙且翘曲度大,粗糙度分别为0.15和0.016μm,翘曲度分别为147和109μm;经过抛光和湿法腐蚀后的样品无表面损伤,粗糙度均小于0.01μm,硅片翘曲度低于60μm。 展开更多
关键词 硅晶圆 背面减薄 损伤 抛光 湿法腐蚀
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铝诱导多晶硅薄膜籽晶层的电学性质 被引量:1
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作者 吴强 陈诺夫 +5 位作者 辛雅焜 黄添懋 陈吉堃 牟潇野 杨博 白一鸣 《微纳电子技术》 CAS 北大核心 2014年第10期623-627,共5页
利用磁控溅射系统在玻璃衬底上制备出具有玻璃∕铝∕非晶硅的多层膜结构样品,然后在管式退火炉中以一定的温度退火,使非晶硅晶化形成多晶硅薄膜籽晶层。扫描电子显微镜(SEM)及光学显微镜测试表明,铝诱导结晶后样品中的铝层已被完全置换... 利用磁控溅射系统在玻璃衬底上制备出具有玻璃∕铝∕非晶硅的多层膜结构样品,然后在管式退火炉中以一定的温度退火,使非晶硅晶化形成多晶硅薄膜籽晶层。扫描电子显微镜(SEM)及光学显微镜测试表明,铝诱导结晶后样品中的铝层已被完全置换为连续并且厚度均匀的多晶硅层,多晶硅晶粒的平均尺寸为23μm。喇曼光谱测试和X射线衍射(XRD)分析表明,多晶硅薄膜籽晶层具有良好的结晶质量,并且具有高度的(111)择优取向。霍尔测试结果表明,铝诱导多晶硅薄膜籽晶层属于高浓度p型掺杂,掺杂浓度达到了1018/cm3。分析认为铝在非晶硅晶化过程中不仅扮演了诱导金属的角色,还起到了掺杂的作用。 展开更多
关键词 铝诱导 多晶硅薄膜 籽晶层 择优取向 掺杂
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微晶硅薄膜太阳电池中孵化层研究 被引量:3
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作者 张晓丹 赵颖 +5 位作者 高艳涛 朱锋 魏长春 孙建 耿新华 熊绍珍 《Journal of Semiconductors》 EI CAS CSCD 北大核心 2006年第6期1030-1033,共4页
对甚高频等离子体增强化学气相沉积技术制备的微晶硅薄膜太阳电池进行了研究.喇曼测试结果显示:微晶硅薄膜太阳电池在p/i界面存在着一定的非晶孵化层.孵化层的厚度随硅烷浓度的增加或辉光功率的降低而增大.可以通过适当的硅烷浓度或适... 对甚高频等离子体增强化学气相沉积技术制备的微晶硅薄膜太阳电池进行了研究.喇曼测试结果显示:微晶硅薄膜太阳电池在p/i界面存在着一定的非晶孵化层.孵化层的厚度随硅烷浓度的增加或辉光功率的降低而增大.可以通过适当的硅烷浓度或适当的辉光功率来降低孵化层的厚度. 展开更多
关键词 微晶硅薄膜太阳电池 孵化层 喇曼光谱
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8英寸薄层硅外延片的均匀性控制方法 被引量:9
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作者 张志勤 袁肇耿 薛宏伟 《半导体技术》 CSCD 北大核心 2017年第7期531-535,560,共6页
8英寸(1英寸=2.54 cm)薄层硅外延片的不均匀性是制约晶圆芯片良率水平的瓶颈之一。研究了硅外延工艺过程中影响薄外延层厚度和电阻率均匀性的关键因素,在保证不均匀性小于3%的前提下,外延层厚度和电阻率形成中间低、边缘略高的"碗... 8英寸(1英寸=2.54 cm)薄层硅外延片的不均匀性是制约晶圆芯片良率水平的瓶颈之一。研究了硅外延工艺过程中影响薄外延层厚度和电阻率均匀性的关键因素,在保证不均匀性小于3%的前提下,外延层厚度和电阻率形成中间低、边缘略高的"碗状"分布可有效提高晶圆的良率水平。通过调整生长温度和氢气体积流量可实现外延层厚度的"碗状"分布,但调整温区幅度不得超过滑移线的温度门槛值。通过提高边缘温度来提高边缘10 mm和6 mm的电阻率,同时提高生长速率以提高边缘3 mm的电阻率,获得外延层电阻率的"碗状"分布,8英寸薄层硅外延片的的边缘离散现象得到明显改善,产品良率也有由原来的94%提升至98.5%,进一步提升了8英寸薄层硅外延片产业化良率水平。 展开更多
关键词 8英寸硅外延片 薄层外延 外延层厚度 电阻率 不均匀性 “碗状”分布
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石墨衬底上具有(220)/(400)择优取向多晶硅薄膜的制备及性质(英文) 被引量:3
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作者 辛雅焜 陈诺夫 +6 位作者 吴强 白一鸣 陈吉堃 何海洋 李宁 黄添懋 施辉伟 《功能材料》 EI CAS CSCD 北大核心 2015年第4期4153-4158,共6页
在石墨衬底上分别制备了具有(220)和(400)择优取向的多晶硅薄膜。首先利用磁控溅射技术直接在石墨衬底上制备非晶硅薄膜层,以及先制备Zn O过渡层,再在Zn O过渡层上制备非晶硅薄膜层;然后采用快速退火法对非晶硅薄膜晶化,使其形成多晶硅... 在石墨衬底上分别制备了具有(220)和(400)择优取向的多晶硅薄膜。首先利用磁控溅射技术直接在石墨衬底上制备非晶硅薄膜层,以及先制备Zn O过渡层,再在Zn O过渡层上制备非晶硅薄膜层;然后采用快速退火法对非晶硅薄膜晶化,使其形成多晶硅薄膜籽晶层。XRD测试表明,未引入Zn O过渡层的多晶硅薄膜籽晶层具有高度(220)择优取向,而引入Zn O过渡层的多晶硅薄膜籽晶层具有高度(400)择优取向;最后在多晶硅籽晶层上通过对流辅助化学气相沉积(Co CVD)制备多晶硅薄膜。根据SEM、XRD、拉曼测试表明,多晶硅薄膜的性质延续了多晶硅籽晶层的性质,未引入Zn O过渡层的样品,具有高度(220)择优取向。引入Zn O过渡层后的样品,具有高度(400)择优取向,(400)择优取向的转变有利于后续多晶硅薄膜太阳电池的制作。同时对Si(220)和Si(400)择优取向的形成原因做了初步分析。 展开更多
关键词 多晶硅薄膜 石墨衬底 籽晶层 氧化锌 择优取向 对流辅助化学气相沉积
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带本征薄层硅异质结HIT太阳能电池的研究与发展 被引量:2
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作者 文国知 范吉军 李相虎 《武汉轻工大学学报》 2017年第2期1-7,共7页
介绍了带本征薄层硅异质结HIT太阳能电池的研究与产业化进程。阐述了提高硅异质结HIT太阳能电池光电转换效率的关键技术,如单晶硅片表面的织构化技术、异质结界面的钝化技术、栅电极制备技术和双面电池技术。最后,介绍了基于量子限域效... 介绍了带本征薄层硅异质结HIT太阳能电池的研究与产业化进程。阐述了提高硅异质结HIT太阳能电池光电转换效率的关键技术,如单晶硅片表面的织构化技术、异质结界面的钝化技术、栅电极制备技术和双面电池技术。最后,介绍了基于量子限域效应的硅量子点异质结HIT太阳能电池的设计理论及研究进展。 展开更多
关键词 硅异质结 本征层 钝化 转换效率 太阳能电池
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薄硅层阶梯埋氧PSOI高压器件新结构
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作者 吴丽娟 胡盛东 +1 位作者 张波 李肇基 《固体电子学研究与进展》 CAS CSCD 北大核心 2010年第3期327-332,共6页
基于介质电场增强ENDIF理论,提出了一种薄硅层阶梯埋氧型部分SOI(SBPSOI)高压器件结构。埋氧层阶梯处所引入的电荷不仅增强了埋层介质电场,而且对有源层中的电场进行调制,使电场优化分布,两者均提高器件的击穿电压。详细分析器件耐压与... 基于介质电场增强ENDIF理论,提出了一种薄硅层阶梯埋氧型部分SOI(SBPSOI)高压器件结构。埋氧层阶梯处所引入的电荷不仅增强了埋层介质电场,而且对有源层中的电场进行调制,使电场优化分布,两者均提高器件的击穿电压。详细分析器件耐压与相关结构参数的关系,在埋氧层为2μm,耐压层为0.5μm时,其埋氧层电场提高到常规结构的1.5倍,击穿电压提高53.5%。同时,由于源极下硅窗口缓解SOI器件自热效应,使得在栅电压15V,漏电压30V时器件表面最高温度较常规SOI降低了34.76K。 展开更多
关键词 薄硅层 介质场增强 阶梯埋氧 耐压 调制 自热效应
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原子层沉积Al_2O_3薄膜钝化n型单晶硅表面的研究 被引量:3
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作者 李想 颜钟惠 +1 位作者 刘阳辉 竺立强 《材料导报》 EI CAS CSCD 北大核心 2013年第8期40-43,共4页
以三甲基铝(TMA)和水为反应源,采用原子层沉积(ALD)技术在n型单晶硅表面沉积15nm、30nm和100nm的Al2O3薄膜,并对样品进行快速退火(RTA)处理。采用少子寿命测试仪测试样品的有效少子寿命,获得了表面复合速率(SRV),通过X射线光电子能谱(X... 以三甲基铝(TMA)和水为反应源,采用原子层沉积(ALD)技术在n型单晶硅表面沉积15nm、30nm和100nm的Al2O3薄膜,并对样品进行快速退火(RTA)处理。采用少子寿命测试仪测试样品的有效少子寿命,获得了表面复合速率(SRV),通过X射线光电子能谱(XPS)分析了薄膜的化学成分,在此基础上研究了薄膜厚度及退火条件对钝化效果的影响,并分析了钝化机理。结果表明:ALD技术制备的Al2O3薄膜经退火后可使n型单晶硅SRV值降低到7cm/s,表面钝化效果显著。 展开更多
关键词 太阳能电池 晶体硅钝化 原子层沉积 AL2O3薄膜
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