An improved arctangent algorithm based on phase-locked loop for heterodyne detection system

We present an ameliorated arctangent algorithm based on phase-locked loop for digital Doppler signal processing,utilized within the heterodyne detection system. We define the error gain factor given by the approximation of Taylor expansion by means of a comparison of the measured values and true values. Exact expressions are derived for the amplitude error of two in-phase & quadrature signals and the frequency error of the acousto-optic modulator. Numerical simulation results and experimental results make it clear that the dynamic instability of the intermediate frequency signals leads to cumulative errors, which will spiral upward. An improved arctangent algorithm for the heterodyne detection is proposed to eliminate the cumulative errors and harmonic components. Depending on the narrow-band filter, our experiments were performed to realize the detectable displacement of 20 nm at a detection distance of 20 m. The aim of this paper is the demonstration of the optimized arctangent algorithm as a powerful approach to the demodulation algorithm, which will advance the signal-to-noise ratio and measurement accuracy of the heterodyne detection system.

Design of radiation hard phase-locked loop at 2.5 GHz using SOS-CMOS

A radiation hard phase-locked loop （PLL） is designed at 2.5 GHz using silicon on sapphire complementary metal-oxide-semiconductor process. Radiation hardness is achieved through improving circuit design without sacrificing real estate. Stability is guaranteed by a fully self-bias architecture. The lock time of PLL is minimized by maximizing the loop bandwidth. Frequency tuning range of voltage controlled oscillator is significantly enhanced by a novel load configuration. In addition, multiple bias stages, asynchronous frequency divider, and silicon on sapphire process jointly make the proposed PLL more radiation hard. Layout of this PLL is simulated by Cadence Spectre RF under both single event effect and total induced dose effect. Simulation results demonstrate excellent stability, lock time 〈 600 ns, frequency tuning range [1.57 GHz, 3.46 GHz], and jitter 〈 12 ps. Through comparison with PLLs in literatures, the PLL is especially superior in terms of lock time and frequency tuning range performances.

A novel high precision Doppler frequency estimation method based on the third-order phase-locked loop

In deep space exploration,many engineering and scientific requirements require the accuracy of the measured Doppler frequency to be as high as possible.In our paper,we analyze the possible frequency measurement points of the third-order phase-locked loop(PLL)and find a new Doppler measurement strategy.Based on this finding,a Doppler frequency measurement algorithm with significantly higher measurement accuracy is obtained.In the actual data processing,compared with the existing engineering software,the accuracy of frequency of 1 second integration is about 5.5 times higher when using the new algorithm.The improved algorithm is simple and easy to implement.This improvement can be easily combined with other improvement methods of PLL,so that the performance of PLL can be further improved.

A LOW POWER TIME-TO-DIGITAL CONVERTER FOR ALL-DIGITAL PHASE-LOCKED LOOP

Time-to-Digital Converter (TDC) is a key block used as the phase/frequency detector in an All-Digital Phase-Locked Loop (ADPLL). Usually, it occupies a large proportion of ADPLL's total power consumption up to about 30% to 40%. In this paper, the detailed power consumption of different components in the TDC is analyzed. A Power Management Block (PMB) is presented for the TDC to reduce its power consumption. A 24-bits TDC core with the proposed PMB is implemented in HJTC 0.18 μm CMOS technology. Simulation results show that up to 84% power reduction is achieved using our proposed technique.

Novel Control Strategy for Multi-Level Active Power Filter without Phase-Locked-Loop

Active power filter (APF) using novel virtual line-flux-linkage oriented control strategy can not only realizes no phase-locked-loop (PLL) control, but also achieves a good inhibitory effect to interfere. However, there are some problems in the conventional method, such as the error of amplitude, the shift of phase angle and the non-determinacy of initial oriented angle. In this paper, two one-order low-pass filters are adopted instead of the pure integrator in the virtual line-flux-linkage observer, which can steady the phase and amplitude. Furthermore, an original scheme of harmonics detection under the rotating coordinate is advanced based on the simplified space vector pulse width modulation (SVPWM) strategy. Meanwhile, by using the new SVPWM algorithm, the voltage space vector diagram of the three-level inverter can be simplified and applied into that of two-level inverter, and this makes the control for Neutral Point potential easier.

A Digital Phase Locked Loop Speed Control of Three Phase Induction Motor Drive: Performances Analysis

This paper deals with performance analysis and implementation of a three phase inverter fed induction motor (IM) drive system. The closed loop control scheme of the drive utilizes the Digital Phase Locked Loop (DPLL). The DPLL is safely implemented all around the well known integrated circuit DPLL 4046. An ex-perimental verification is carried out on one kw scalar controlled IM system drives for a wide range of speeds and loads appliance. This presents a simple and high performance solution for industrial applications.

Fast-Lock Low-Jitter PLL with a Simple Phase-Frequency Detector

A fast-locking, low-jitter, phase-locked loop （PLL） with a simple phase-frequency detector is proposed. The phase-frequency detector is composed of only two XOR gates. It simultaneously achieves low jitter and short locking time. The voltage-controlled oscillator within the PLL consists of four-stage ring oscillators which are coupled to each other and oscillate with the same frequency and a phase shift of 45. The PLL is fabricated in 0. 1Stem CMOS technology. The measured phase noise of the PLL output at 500kHz offset from the 5GHz center frequency is - 102.6dBc/Hz. The circuit exhibits a capture range of 280MHz and a low RMS jitter of 2.06ps. The power dissipation excluding the output buffers is only 21.6roW at a 1.8V supply.

Low phase noise millimeter wave monolithic integrated phase locked-loop

A Monolithic integrated phase locked-loop （PLL） with a low phase noise is proposed in this paper. Several techniques are utilized to improve the performance of the PLL which works at the milli- meter-wave band. The on-chip high-Q eoplanar waveguides （CPWs） are utilized in the resonant tank and the differential current amplifier with a resonator is used to realize the VCO. In the output buffer circuit, several stages of cascaded source-followers connect and differential amplifiers are adopted to improve the driving capability of the PLL＇ s output signals. An improved analog multiplier topology is also used in the PD circuit to improve the gain of the PD. The proposed PLL is realized with a 0.2p, m GaAs pseudomorphie high electron mobility transistor （PHEMT） process. At 10 kHz offset from the center frequency, the measured output phase noise of the PLL output is only -88.83dBc/Hz. The circuit exhibits a low root mean sauare （RMS） litter of 1.68Ds.

Hybrid phase-locked loop with fast locking time and low spur in a 0.18-μm CMOS process

We propose a novel hybrid phase-locked loop （PLL） architecture for overcoming the trade-off between fast locking time and low spur. To reduce the settling time and meanwhile suppress the reference spurs, we employ a wide-band single-path PLL and a narrow-band dual-path PLL in a transient state and a steady state, respectively, by changing the loop bandwidth according to the gain of voltage controlled oscillator （VCO） and the resister of the loop filter. The hybrid PLL is implemented in a 0.18-μm complementary metal oxide semiconductor （CMOS） process with a total die area of 1.4×0.46 mm2. The measured results exhibit a reference spur level of lower than -73 dB with a reference frequency of 10 MHz and a settling time of 20 μs with 40 MHz frequency jump at 2 GHz. The total power consumption of the hybrid PLL is less than 27 mW with a supply voltage of 1.8 V.

THE DESIGN OF AN ALL-DIGITAL PHASE-LOCKED LOOP WITH LOW JITTER BASED ON ISF ANALYSIS

A low jitter All-Digital Phase-Locked Loop （ADPLL） used as a clock generator is designed. The Digital-Controlled Oscillator （DCO） for this ADPLL is a seven-stage ring oscillator with the delay of each stage changeable. Based on the Impulse Sensitivity Function （ISF） analysis, an effective way is proposed to reduce the ADPLL＇s jitter by the careful design of the sizes of the inverters used in the DCO with a simple architecture other than a complex one. The ADPLL is implemented in a 0.18μm CMOS process with 1.SV supply voltage, occupies 0.046mm^2 of on-chip area. According to the measured results, the ADPLL can operate from 108MHz to 304MHz, and the peak-to-peak jitter is 139ps when the DCO＇s output frequency is 188MHz.

A Static Phase Offset Reduction Technique for Multiplying Delay-Locked Loop

Static phase offset (SPO) in conventional multiplying delay-locked loops (MDLLs) dramatically degrades the deterministic jitter performance. To overcome the issue, this paper presents a new SPO reduction technique for MDLLs. The technique is based on the observation that the SPO of MDLL is mainly caused by the non-idealities on charge pump (e.g. sink and source current mismatch), and control line (e.g. gate leakage of loop filter and voltage controlled delay line (VCDL) control circuit). With a high gain stage inserting between phase detector/phase frequency detector (PD/PFD) and charge pump, the equivalent SPO has been decreased by a factor equal to the gain of the gain stage. The effectiveness of the proposed technique is validated by a Simulink model of MDLL. The equivalent SPO is measured by the power level of reference spur.

Multi-Order Intermittent Chaotic Synchronization of Closed Phase Locked Loop

For the model of a Closed Phase Locked Loop (CPLL) communication System consists of both the transmission and receiver ends. This model is considered to be in a multi-order intermittent chaotic state. The chaotic signals are then synchronized along side with our system. This chaotic synchronization will be demonstrated and furthermore, a modulation will be formed to examine the system if it will perfectly reconstruct or not. Finally we will demonstrate the synchronization conditions of the system.

Phase-Locked Loop Based Cancellation of ECG Power Line Interference

Power line(PL)interference is one significant artifact in electrocardiography(ECG)that needs to be reduced to ensure accurate recording of cardiac signals.Because PL interference is non-stationary and has varying frequency,phase,and amplitude in ECG measurement,adaptive techniques are often necessary to track and cancel the interference.In this paper we present a phase-locked loop(PLL)-based adaptive filter to cancel PL interference.The PLL obtains the reference signal that is fed into the adaptive filter to remove the PL interference at the central frequency of 50 Hz.It is found that the technique can effectively cancel PL interference in real ECG signals and,when compared with some existing techniques such as least mean squares(LMS)adaptive filter,the new technique produces better results in terms of signal-to-interference ratio(SIR).

Dynamic Free-Spectral-Range Measurement for Fiber Resonator Based on Digital-Heterodyne Optical Phase-Locked Loop

We propose a novel scheme, based on digital-heterodyne optical phase-locked loop with whole-fiber circuit, to dynamically measure the free-spectral-range of a fiber resonator. The optical phase-locked loop is established with a differential frequency-modulation module consists of a pair of acousto-optic modulators. The resonance-tracking loop is derived with the Pound-Drever-Hall technique for locking the heterodyne frequency of the OPLL on the frequency difference between adjacent resonance modes. A stable locking accuracy of about 7 × 10?9 and a dynamic locking accuracy of about 5 × 10?8 are achieved with the FSR of 8.155 MHz, indicating a bias stability of the resonator fiber optic gyro of about 0.1?/h with 10 Hz bandwidth. In addition, the thermal drift coefficient of the FSR is measured as 0.1 Hz/?C. This shows remarkable potential for realizing advanced optical measurement systems, such as the resonant fiber optic gyro, and so on.

A Low Phase Noise Ring-VCO Based PLL Using Injection Locking for ZigBee Applications

A low power low phase noise frequency synthesizer with subharmonic injection locking is proposed for ZigBee applications. The PLL is based on a ring VCO to decrease area and production cost. In order to improve phase noise performance, a high frequency injection signal of which frequency varies with channel number is used. The circuit is designed in TSMC 0.18 μm CMOS technology and simulated in ADS (Advanced Design System). The phase noise at 3.5 and 10 MHz offsets is -116 and -118 dBc/Hz, respectively, and total circuit consumes 2.2 mA current.

A sapphire fibre thermal probe based on fast Fourier transform and phase-lock loop

A sapphire fibre thermal probe with Cr^3＋ ion-doped end is developed by using the laser heated pedestal growth method. The fluorescence thermal probe offers advantages of compact structure, high performance and ability to withstand high temperature in a detection range from room temperature to 450℃. Based on the fast Fourier transform （FFT）, the fluorescence lifetime is obtained from the tangent function of phase angle of the non-zeroth terms in the FFT result. This method has advantages such as quick calculation, high accuracy and immunity to the background noise. This FFT method is compared with other traditional fitting methods, indicating that the standard deviation of the FFT method is about half of that of the Prony method and about 1/6 of that of the log-fit method. And the FFT method is immune to the background noise involved in a signal. So, the FFT method is an excellent way of processing signals. In addition, a phase-lock amplifier can effectively suppress the noise.

计及风电PSS与PLL耦合对功角振荡影响的DFIG控制参数协调优化

双馈感应发电机(doubly fed induction generator,DFIG)装设电力系统稳定器(power system stabilizer,PSS),有助于抑制同步发电机间功角振荡,但抑制效果受DFIG锁相环(phase-locked loop,PLL)跟踪误差影响。考虑PSS与PLL耦合特性对功角振荡的影响,提出改善振荡抑制效果的DFIG控制参数协调优化算法。首先基于DFIG有功控制的分解等效结构绘制DFIG-PSS与锁相误差的耦合路径,提出耦合特性解析表达。然后建立耦合解析表达对控制参数的轨迹灵敏度向量,以向量2-范数之比定义耦合强度,量化耦合特性对功角振荡的影响程度。最后基于耦合强度指标,提出带有PLL参数动态不等式约束的多步优化模型,以协调DFIG控制参数取值,提高并网系统对功角振荡的抑制效果。仿真结果证实了耦合特性对功角振荡的影响,验证了所提协调优化算法的有效性。

三相电压不平衡下DDSRF-PLL与DSOGI-PLL的锁相误差检测与补偿方法

由于高渗透的分布式电源、多样化的负荷类型以及电网故障等因素,并网点三相电压不仅存在幅值不平衡,而且会出现相位不平衡现象。这种情况下,广泛应用的解耦双同步坐标系锁相环(DDSRF-PLL)和双二阶广义积分器锁相环(DSOGI-PLL)无法获得精确的同步信息。为此,该文在论证这两种锁相环具有理论等价性的基础上,阐释三相电压不平衡与锁相误差的内在关系,进而提出一种锁相误差的补偿方法,实现幅值和相位不平衡下的准确锁相。所提方法仅需对电压采样值进行简单计算即可获得不平衡相位和锁相误差,实现开环相位补偿,无需修改原有锁相结构,具有良好的拓展性。最后,通过仿真和实验验证了所提方法的有效性。

考虑PLL频率限幅的MMC风电场故障恢复同步稳定性

基于模块化多电平换流器的风电场在发生交流短路故障时,可能会出现风机变流器锁相环(phaselockloop,PLL)同步失稳问题。当前研究集中在故障阶段同步稳定机理研究和改善方案,但是缺乏故障切除后恢复阶段PLL同步稳定研究。该文研究恢复阶段PLL同步稳定问题,考虑到故障阶段可能出现同步失稳、以及PLL频率振荡过冲导致限幅,建立了考虑PLL频率限幅的系统暂态分析模型;引入恢复稳定域的概念,并且研究了PLL频率限幅、恢复阶段风机电流、电压(恢复速率)、PLL-PI参数对稳定域的影响;基于恢复稳定域提出了参数优化和PLL软件复位的恢复稳定改善措施;最后通过仿真验证了理论分析的合理性。

PLL DEMODULATION TECHNIQUE FOR M-RAY POSITION PHASE SHIFT KEYING

The paper presents a kind of transmission system which employs M-ary Position Phase Shift Keying(MPPSK) to send data and Phase Locked Loop(PLL) based techniques for data retrieve.With a single PLL, MPPSK demodulation is achieved, as well as carrier recovery and symbol synchronization.Firstly, MPPSK modulation method is briefly introduced.2PPSK's PSD expression is given with its optimization result.Orthogonal Phase Detector(PD) and static threshold are used for the purpose of wider phase range and simplicity in demodulation.The data rate is alterable, which is 4.65 kbps for 2PPSK and 9.3 kbps for 4PPSK in the paper.Then some indicative comparisons in Signal to Noise Ratio Symbol Error Rate(SNR-SER) are made among 2PPSK, 3PPSK and 4PPSK, of which 4PPSK has proved to be optimal in ten slots each symbol conditions.And finally, it is demonstrated by system simulations that lower than 10-4 Symbol Error Rate(SER) performance can be obtained at 13 dB symbol SNR.