Through-silicon-via crosstalk model and optimization design for three-dimensional integrated circuits

Through-silicon-via （TSV） to TSV crosstalk noise is one of the key factors affecting the signal integrity of three- dimensional integrated circuits （3D ICs）. Based on the frequency dependent equivalent electrical parameters for the TSV channel, an analytical crosstalk noise model is established to capture the TSV induced crosstalk noise. The impact of various design parameters including insulation dielectric, via pitch, via height, silicon conductivity, and terminal impedance on the crosstalk noise is analyzed with the proposed model. Two approaches are proposed to alleviate the TSV noise, namely, driver sizing and via shielding, and the SPICE results show 241 rnV and 379 mV reductions in the peak noise voltage, respectively.

Pixelated non-volatile programmable photonic integrated circuits with 20-level intermediate states

Multi-level programmable photonic integrated circuits(PICs)and optical metasurfaces have gained widespread attention in many fields,such as neuromorphic photonics,opticalcommunications,and quantum information.In this paper,we propose pixelated programmable Si_(3)N_(4)PICs with record-high 20-level intermediate states at 785 nm wavelength.Such flexibility in phase or amplitude modulation is achieved by a programmable Sb_(2)S_(3)matrix,the footprint of whose elements can be as small as 1.2μm,limited only by the optical diffraction limit of anin-house developed pulsed laser writing system.We believe our work lays the foundation for laser-writing ultra-high-level(20 levels and even more)programmable photonic systems and metasurfaces based on phase change materials,which could catalyze diverse applications such as programmable neuromorphic photonics,biosensing,optical computing,photonic quantum computing,and reconfigurable metasurfaces.

Carbon nanotube integrated circuit technology:purification,assembly and integration

As the manufacturing process of silicon-based integrated circuits(ICs)approaches its physical limit,the quantum effect of silicon-based field-effect transistors(FETs)has become increasingly evident.And the burgeoning carbon-based semiconductor technology has become one of the most disruptive technologies in the post-Moore era.As one-dimensional nanomaterials,carbon nanotubes(CNTs)are far superior to silicon at the same technology nodes of FETs because of their excellent electrical transport and scaling properties,rendering them the most competitive material in the next-generation ICs technology.However,certain challenges impede the industrialization of CNTs,particularly in terms of material preparation,which significantly hinders the development of CNT-based ICs.Focusing on CNT-based ICs technology,this review summarizes its main technical status,development trends,existing challenges,and future development directions.

Study on Si-SiGe Three-Dimensional CMOS Integrated Circuits

Based on the physical characteristics of SiGe material,a new three-dimensional （3D） CMOS IC structure is proposed,in which the first device layer is made of Si material for nMOS devices and the second device layer is made of Six Ge1- x material for pMOS. The intrinsic performance of ICs with the new structure is then limited by Si nMOS.The electrical characteristics of a Si-SiGe 3D CMOS device and inverter are all simulated and analyzed by MEDICI. The simulation results indicate that the Si-SiGe 3D CMOS ICs are faster than the Si-Si 3D CMOS ICs. The delay time of the 3D Si-SiGe CMOS inverter is 2-3ps,which is shorter than that of the 3D Si-Si CMOS inverter.

Reduction of signal reflection along through silicon via channel in high-speed three-dimensional integration circuit

The through silicon via （TSV） technology has proven to be the critical enabler to realize a three-dimensional （3D） gigscale system with higher performance but shorter interconnect length. However, the received digital signal after trans- mission through a TSV channel, composed of redistribution layers （RDLs）, TSVs, and bumps, is degraded at a high data-rate due to the non-idealities of the channel. We propose the Chebyshev multisection transformers to reduce the signal reflec- tion of TSV channel when operating frequency goes up to 20 GHz, by which signal reflection coefficient （$11） and signal transmission coefficient （$21） are improved remarkably by 150% and 73.3%, respectively. Both the time delay and power dissipation are also reduced by 4% and 13.3%, respectively. The resistance-inductance-conductance-capacitance （RLGC） elements of the TSV channel are iterated from scattering （S）-parameters, and the proposed method of weakening the signal reflection is verified using high frequency simulator structure （HFSS） simulation software by Ansoft.

Emerging MoS_(2)Wafer-Scale Technique for Integrated Circuits

As an outstanding representative of layered materials,molybdenum disulfide(MoS_(2))has excellent physical properties,such as high carrier mobility,stability,and abundance on earth.Moreover,its reasonable band gap and microelectronic compatible fabrication characteristics makes it the most promising candidate in future advanced integrated circuits such as logical electronics,flexible electronics,and focal-plane photodetector.However,to realize the all-aspects application of MoS_(2),the research on obtaining high-quality and large-area films need to be continuously explored to promote its industrialization.Although the MoS_(2)grain size has already improved from several micrometers to sub-millimeters,the high-quality growth of wafer-scale MoS_(2)is still of great challenge.Herein,this review mainly focuses on the evolution of MoS_(2)by including chemical vapor deposition,metal–organic chemical vapor deposition,physical vapor deposition,and thermal conversion technology methods.The state-of-the-art research on the growth and optimization mechanism,including nucleation,orientation,grain,and defect engineering,is systematically summarized.Then,this review summarizes the wafer-scale application of MoS_(2)in a transistor,inverter,electronics,and photodetectors.Finally,the current challenges and future perspectives are outlined for the wafer-scale growth and application of MoS_(2).

Three-Dimensional Cooperative Localization via Space-Air-Ground Integrated Networks

The space-air-ground integrated network(SAGIN)combines the superiority of the satellite,aerial,and ground communications,which is envisioned to provide high-precision positioning ability as well as seamless connectivity in the 5G and Beyond 5G(B5G)systems.In this paper,we propose a three-dimensional SAGIN localization scheme for ground agents utilizing multi-source information from satellites,base stations and unmanned aerial vehicles(UAVs).Based on the designed scheme,we derive the positioning performance bound and establish a distributed maximum likelihood algorithm to jointly estimate the positions and clock offsets of ground agents.Simulation results demonstrate the validity of the SAGIN localization scheme and reveal the effects of the number of satellites,the number of base stations,the number of UAVs and clock noise on positioning performance.

A Thermal-Conscious Integrated Circuit Power Model and Its Impact on Dynamic Voltage Scaling Techniques

We propose a novel thermal-conscious power model for integrated circuits that can accurately predict power and temperature under voltage scaling. Experimental results show that the leakage power consumption is underestimated by 52 % if thermal effects are omitted. Furthermore, an inconsistency arises when energy and temperature are simultaneously optimized by dynamic voltage scaling. Temperature is a limiting factor for future integrated circuits,and the thermal optimization approach can attain a temperature reduction of up to 12℃ with less than 1.8% energy penalty compared with the energy optimization one.

Integrated circuit for single channel neural signal regeneration

Based on the 4-channel neural signal regeneration system which is realized by using discrete devices and successfully used for in-vivo experiments on rats and rabbits, a single channel neural signal regeneration integrated circuit （IC）is designed and realized in CSMC ＇ s 0. 6 μm CMOS （ complementary metal-oxide-semiconductor transistor ） technology. The IC consists of a neural signal detection circuit with an adjustable gain, a buffer, and a function electrical stimulation （FES） circuit. The neural signal regenerating IC occupies a die area of 1.42 mm × 1.34 mm. Under a dual supply voltage of ±2. 5 V, the DC power consumption is less than 10 mW. The on-wafer measurement results are as follows： the output resistor is 118 ml）, the 3 dB bandwidth is greater than 30 kHz, and the gain can be variable from 50 to 90 dB. The circuit is used for in-vivo experiments on the rat＇ s sciatic nerve as well as on the spinal cord with the cuff type electrode array and the twin-needle electrode. The neural signal is successfully regenerated both on a rat＇ s sciatic nerve bundle and on the spinal cord.

Integration system research and development for three-dimensional laser scanning information visualization in goaf

An integration processing system of three-dimensional laser scanning information visualization in goaf was developed. It is provided with multiple functions, such as laser scanning information management for goaf, cloud data de-noising optimization, construction, display and operation of three-dimensional model, model editing, profile generation, calculation of goaf volume and roof area, Boolean calculation among models and interaction with the third party soft ware. Concerning this system with a concise interface, plentiful data input/output interfaces, it is featured with high integration, simple and convenient operations of applications. According to practice, in addition to being well-adapted, this system is favorably reliable and stable.

Test system of the front-end readout for an application-specific integrated circuit for the water Cherenkov detector array at the large high-altitude air shower observatory

The water Cherenkov detector array(WCDA) is an important part of the large high-altitude air shower observatory(LHAASO),which is in a research and development phase.The central scientific goal of LHAASO is to explore the origin of high-energy cosmic rays of the universe and to push forward the frontier of new physics.To simplify the WCDA's readout electronics,a prototype of a front-end readout for an application-specific integrated circuit(ASIC) is designed based on the timeover-threshold method to achieve charge-to-time conversion.High-precision time measurement and charge measurement are necessary over a full dynamic range[1-4000photoelectrons(P.E.)].To evaluate the performance of this ASIC,a test system is designed that includes the front-end ASIC test module,digitization module,and test software.The first module needs to be customized for different ASIC versions,whereas the digitization module and test software are tested for general-purpose use.In the digitization module,a field programmable gate array-based time-todigital converter is designed with a bin size of 333 ps,which also integrates an inter-integrated circuit to configure the ASIC test module,and a universal serial bus interface is designed to transfer data to the remote computer.Test results indicate that the time resolution is better than 0.5 ns,and the charge resolution is better than 30%root mean square(RMS) at 1 P.E.and 3%RMS at 4000 P.E.,which are beyond the application requirements.

Real-time in situ three-dimensional integral videography and surgical navigation using augmented reality: a pilot study

To evaluate the feasibility and accuracy of a three-dimensional augmented reality system incorporating integral videography for imaging oral and maxillofacial regions, based on preoperative computed tomography data. Three-dimensional surface models of the jawbones, based on the computed tomography data, were used to create the integral videography images of a subject＇s maxillofacial area. The three-dimensional augmented reality system （integral videography display, computed tomography, a position tracker and a computer） was used to generate a three-dimensional overlay that was projected on the surgical site via a half-silvered mirror. Thereafter, a feasibility study was performed on a volunteer. The accuracy of this system was verified on a solid model while simulating bone resection. Positional registration was attained by identifying and tracking the patient/surgical instrument＇s position. Thus, integral videography images of jawbones, teeth and the surgical tool were superimposed in the correct position. Stereoscopic images viewed from various angles were accurately displayed. Change in the viewing angle did not negatively affect the surgeon＇s ability to simultaneously observe the three-dimensional images and the patient, without special glasses. The difference in three-dimensional position of each measuring point on the solid model and augmented reality navigation was almost negligible （〈1 mm）; this indicates that the system was highly accurate. This augmented reality system was highly accurate and effective for surgical navigation and for overlaying a three-dimensional computed tomography image on a patient＇s surgical area, enabling the surgeon to understand the positional relationship between the preoperative image and the actual surgical site, with the naked eye.

High density Al2O3/TaN-based metal-insulatormetal capacitors in application to radio equency integrated circuits

Metal-insulator-metal （MIM） capacitors with atomic-layer-deposited Al2O3 dielectric and reactively sputtered TaN electrodes in application to radio frequency integrated circuits have been characterized electrically. The capacitors exhibit a high density of about 6.05 fF/μm^2, a small leakage current of 4.8 × 10^-8 A/cm^2 at 3 V, a high breakdown electric field of 8.61 MV/cm as well as acceptable voltage coefficients of capacitance （VCCs） of 795 ppm/V2 and 268ppm/V at 1 MHz. The observed properties should be attributed to high-quality Al2O3 film and chemically stable TaN electrodes. Further, a logarithmically linear relationship between quadratic VCC and frequency is observed due to the change of relaxation time with carrier mobility in the dielectric. The conduction mechanism in the high field ranges is dominated by the Poole-Frenkel emission, and the leakage current in the low field ranges is likely to be associated with trap-assisted tunnelling. Meanwhile, the Al2O3 dielectric presents charge trapping under low voltage stresses, and defect generation under high voltage stresses, and it has a hard-breakdown performance.

Hybrid material integration in silicon photonic integrated circuits

Hybrid integration ofⅢ-Ⅴand ferroelectric materials is being broadly adopted to enhance functionalities in silicon photonic integrated circuits(PICs).Bonding and transfer printing have been the popular approaches for integration of III–V gain media with silicon PICs.Similar approaches are also being considered for ferroelectrics to enable larger RF modulation bandwidths,higher linearity,lower optical loss integrated optical modulators on chip.In this paper,we review existing integration strategies ofⅢ-Ⅴmaterials and present a route towards hybrid integration of bothⅢ-Ⅴand ferroelectrics on the same chip.We show that adiabatic transformation of the optical mode between hybrid ferroelectric and silicon sections enables efficient transfer of optical modal energies for maximum overlap of the optical mode with the ferroelectric media,similar to approaches adopted to maximize optical overlap with the gain section,thereby reducing lasing thresholds for hybridⅢ-Ⅴintegration with silicon PICs.Preliminary designs are presented to enable a foundry compatible hybrid integration route of diverse functionalities on silicon PICs.

High performance integrated photonic circuit based on inverse design method

The basic indexes of all-optical integrated photonic circuits include high-density integration,ultrafast response and ultralow energy consumption.Traditional methods mainly adopt conventional micro/nano-structures.The overall size of the circuit is large,usually reaches hundreds of microns.Besides,it is difficult to balance the ultrafast response and ultra-low energy consumption problem,and the crosstalk between two traditional devices is difficult to overcome.Here,we propose and experimentally demonstrate an approach based on inverse design method to realize a high-density,ultrafast and ultra-low energy consumption integrated photonic circuit with two all-optical switches controlling the input states of an all-optical XOR logic gate.The feature size of the whole circuit is only 2.5μm×7μm,and that of a single device is 2μm×2μm.The distance between two adjacent devices is as small as 1.5μm,within wavelength magnitude scale.Theoretical response time of the circuit is 150 fs,and the threshold energy is within 10 fJ/bit.We have also considered the crosstalk problem.The circuit also realizes a function of identifying two-digit logic signal results.Our work provides a new idea for the design of ultrafast,ultra-low energy consumption all-optical devices and the implementation of high-density photonic integrated circuits.

Science Letters:The Moore’s Law for photonic integrated circuits

We formulate a “Moore’s law” for photonic integrated circuits (PICs) and their spatial integration density using two methods. One is decomposing the integrated photonics devices of diverse types into equivalent basic elements, which makes a comparison with the generic elements of electronic integrated circuits more meaningful. The other is making a complex compo- nent equivalent to a series of basic elements of the same functionality, which is used to calculate the integration density for func- tional components realized with different structures. The results serve as a benchmark of the evolution of PICs and we can con- clude that the density of integration measured in this way roughly increases by a factor of 2 per year. The prospects for a continued increase of spatial integration density are discussed.

Simulation realization of skip cycle mode integrated control circuit in the switching power supply with low standby loss

This paper explores and proposes a design solution of an integrated skip cycle mode （SCM） control circuit with a simple structure. The design is simulated and implemented with XD10H-1.0μm modular DIMOS 650 V process. In order to meet the requirement of a wide temperature range and high yields of products, the schematic extracted from the layout is simulated with five process corners at 27℃ and 90℃. Simulation results demonstrate that the proposed integrated circuit is immune to noise and achieves skipping cycle control when switching mode power supply （SMPS） works with low load or without load.

Fabrication of integrated resistors in printed circuit boards

In order to utilize integrated passive technology in printed circuit boards （PCBs）, manufacturing processing for integrated resistors by lamination method was investigated. Integrated resistors fabricated from Ohmega technologies in the experiment were 1 408 pieces per panel with four different patterns A, B, C and D and four resistance values of 25, 50, 75 and 100 fL Six panel per batch and four batches were performed totally. The testing was done for 960 pieces of integrated resistors randomly selected with the same size. The value distribution ranges and the relative standard deviation （RSD） show that the scatter degree of the resistance decreases with the resistor size increasing and/or with the resistance increasing. Patterns D with resistance of 75 and 100% for four patterns have the resistance value variances less than 10%. Patterns C and D with resistance of 100 Ω have the manufacturing tolerance less than 10%. The process capabilities are from about 0.6 to 1.6 for the designed testing patterns, which shows that the integrated resistors fabricated have the potential to be used in multilayer PCBs in the future.

A novel voltage output integrated circuit temperature sensor

The novel integrated circuit (IC) temperature sensor presented in this paper works similarly as a two terminal Zener, has breakdown voltage directly proportional to Kelvin temperature at 10 mV/℃, with typical error of less than ±1.0℃ over a temperature range from -50℃ to +125℃. In addition to all the features that conventional IC temperature sensors have, the new device also has very low static power dissipation ( 0.5 mW ) , low output impedance ( less than 1Ω), excellent stability, high reproducibility, and high precision. The sensor's circuit design and layout are discussed in detail. Applications of the sensor include almost any type of temperature sensing over the range of -50℃-+125℃. The low impedance and linear output of the device make interfacing the readout or control circuitry especially easy. Due to the excellent performance and low cost of this sensor, more applications of the sensor over wide temperature range are expected.

A 330-500 GHz Zero-Biased Broadband Tripler Based on Terahertz Monolithic Integrated Circuits

A 330-500 GHz zero-biased broadband monolithic integrated tripler is reported. The measured results show that the maximum efficiency and the maximum output power are 2% and 194μW at 348 GHz. The saturation characteristic test shows that the output i dB compression point is about -8.5 dBm at 334 GHz and the maximum efficiency is obtained at the point, which is slightly below the 1 dB compression point. Compared with the conventional hybrid integrated circuit, a major advantage of the monolithic integrated circuit is the significant improvement of reliability and consistency. In this work, a terahertz monolithic frequency multiplier at this band is designed and fabricated.