Some Tools to Model Ground or Supply Bounces Induced in and out of Heterogeneous Integrated Circuits

Electrical ground looks simple on a schematic; unfortunately, the actual performance of a circuit is dictated by its layout （and by its printed-circuit-board）. When the ground node moves, system performance suffers and the system radiates electromagnetic interferences. But the understanding of the physics of ground noise can provide an intuitive sense for reducing the problem. Ground bounce can produce transients with amplitudes of volts; most often changing magnetic flux is the cause; in this work, the authors use a Finite-Difference Time-Domain to begin to understand such phenomena. Additionally, predicting substrate cross-talks in mixed-signal circuits has become a critical issue to preserve signal integrity in future integrated systems. Phenomena that involve parasitic signal propagation into the substrate are discussed. A simple methodology to predict the substrate cross-talk and some associated tools are presented. Finally, the authors indicate a stochastic method which could grasp both outer or inner RF （Radio-Frequency） radiations and substrate parasites.

Design and implementation of GM- APD array readout circuit for infrared imaging

Based on an avalanche photodiode（ APD） detecting array working in Geiger mode（ GM-APD）, a high-performance infrared sensor readout integrated circuit（ ROIC） used for infrared 3D（ three-dimensional） imaging is proposed. The system mainly consists of three functional modules, including active quenching circuit（ AQC）, time-to-digital converter（ TDC） circuit and other timing controller circuit. Each AQC and TDC circuit together constitutes the pixel circuit. Under the cooperation with other modules, the current signal generated by the GM-APD sensor is detected by the AQC, and the photon time-of-flight（ TOF） is measured and converted to a digital signal output to achieve a better noise suppression and a higher detection sensitivity by the TDC. The ROIC circuit is fabricated by the CSMC 0. 5 μm standard CMOS technology. The array size is 8 × 8, and the center distance of two adjacent cells is 100μm. The measurement results of the chip showthat the performance of the circuit is good, and the chip can achieve 1 ns time resolution with a 250 MHz reference clock, and the circuit can be used in the array structure of the infrared detection system or focal plane array（ FPA）.

Speeding up carbon nanotube integrated circuits through three-dimensional architecture

Semiconducting carbon nanotube (CNT) field effect transistor (FET) is attractive for constructing three-dimensional (3D) integrated circuits (ICs) because of its low-temperature processes and low power dissipation. However, CNT based 3D ICs reported usually suffered from lower performance than that of monolayer CNT ICs. In this work, we develop a 3D IC technology through integrating multi-layer high performance CNT film FETs into one chip, and show that it promotes the operation speed of CNT based 3D ICs considerably. We also explore the advantage on ICs of 3D architecture, which brings 38% improvement on speed over two-dimensional (2D) one. Specially, we demonstrate the fabrication of 3D five-stage ring-oscillator circuits with an oscillation frequency of up to 680 MHz and stage delay of 0.15 ns, which represents the highest speed of 3D CNT-based ICs.

An optimal stacking order for mid-bond testing cost reduction of 3D IC

In order to solve the problem that the testing cost of the three-dimensional integrated circuit(3D IC)is too high,an optimal stacking order scheme is proposed to reduce the mid-bond test cost.A new testing model is built with the general consideration of both the test time for automatic test equipment(ATE)and manufacturing failure factors.An algorithm for testing cost and testing order optimization is proposed,and the minimum testing cost and optimized stacking order can be carried out by taking testing bandwidth and testing power as constraints.To prove the influence of the optimal stacking order on testing costs,two baselines stacked in sequential either in pyramid type or in inverted pyramid type are compared.Based on the benchmarks from ITC 02,experimental results show that for a 5-layer 3D IC,under different constraints,the optimal stacking order can reduce the test costs on average by 13%and 62%,respectively,compared to the pyramid type and inverted pyramid type.Furthermore,with the increase of the stack size,the test costs of the optimized stack order can be decreased.

基于链式的信号转移冗余TSV方案

三维集成电路(3D IC)带来了诸多的益处,譬如高带宽,低功耗,外形尺寸小。基于硅通孔的三维集成得到了行业的广泛采用。然而,硅通孔的制造过程引入了新的缺陷机制。一个失效的硅通孔会使整个芯片失效,会极大地增加成本。增加冗余硅通孔修复失效硅通孔可能是最有效的提高良率的方法,但是却带来了面积成本。提出了一种基于链式的信号转移冗余方案,输入端从下一分组选择信号硅通孔传输信号。在基于概率模型下,提出的冗余结构良率可以达到99%,同时可以减少冗余TSV的数目。

Circuit modeling and performance analysis of SWCNT bundle 3D interconnects

Metallic carbon nanotubes （CNTs） have been proposed as a promising alternative to Cu interconnects in future integrated circuits （ICs） for their remarkable conductive, mechanical and thermal properties. Compact equiv alent circuit models for single-walled carbon nanotube （SWCNT） bundles are described, and the performance of SWCNT bundle interconnects is evaluated and compared with traditional Cu interconnects at different interconnect levels for through-silicon-via-based three dimensional （3D） ICs. It is shown that at a local level, CNT interconnects exhibit lower signal delay and smaller optimal wire size. At intermediate and global levels, the delay improvement becomes more significant with technology scaling and increasing wire lengths. For 1 mm intermediate and 10 mm global level interconnects, the delay of SWCNT bundles is only 49.49% and 52.82% that of the Cu wires, respec tively.

Integrating MEMS and ICs

The majority of microelectromechanical system(MEMS)devices must be combined with integrated circuits(ICs)for operation in larger electronic systems.While MEMS transducers sense or control physical,optical or chemical quantities,ICs typically provide functionalities related to the signals of these transducers,such as analog-to-digital conversion,amplification,filtering and information processing as well as communication between the MEMS transducer and the outside world.Thus,the vast majority of commercial MEMS products,such as accelerometers,gyroscopes and micro-mirror arrays,are integrated and packaged together with ICs.There are a variety of possible methods of integrating and packaging MEMS and IC components,and the technology of choice strongly depends on the device,the field of application and the commercial requirements.In this review paper,traditional as well as innovative and emerging approaches to MEMS and IC integration are reviewed.These include approaches based on the hybrid integration of multiple chips(multi-chip solutions)as well as system-on-chip solutions based on wafer-level monolithic integration and heterogeneous integration techniques.These are important technological building blocks for the‘More-Than-Moore’paradigm described in the International Technology Roadmap for Semiconductors.In this paper,the various approaches are categorized in a coherent manner,their merits are discussed,and suitable application areas and implementations are critically investigated.The implications of the different MEMS and IC integration approaches for packaging,testing and final system costs are reviewed.

Advanced Process and Electron Device Technology

This article reviews advanced process and electron device technology of integrated circuits,including recent featuring progress and potential solutions for future development.In 5 years,for pushing the performance of fin field-effect transistors(FinFET)to its limitations,several processes and device boosters are provided.Then,the three-dimensional(3 D)integration schemes with alternative materials and device architectures will pave paths for future technology evolution.Finally,it could be concluded that Moore’s law will undoubtedly continue in the next 15 years.