A 900MHz CMOS PLL/Frequency Synthesizer Initialization Circuit

A 900MHz CMOS PLL/frequency synthesizer using current-adjustable charge-pump circuit and on-chip loop filter with initialization circuit is presented.The charge-pump current is insensitive to the changes of temperature and power supply.The value of the charge-pump current can be changed by switches,which are controlled by external signals.Thus the performance of the PLL,such as loop bandwidth,can be changed with the change of the charge-pump current.The loop filter initialization circuit can speed up the PLL when the power is on.A multi-modulus prescaler is used to fulfill the frequency synthesis.The circuit is designed using 0.18μm,1.8V,1P6M standard digital CMOS process.

CMOS analog and mixed-signal phase-locked loops: An overview

CMOS analog and mixed-signal phase-locked loops(PLL)are widely used in varies of the system-on-chips(SoC)as the clock generator or frequency synthesizer.This paper presents an overview of the AMS-PLL,including:1)a brief introduction of the basics of the charge-pump based PLL,which is the most widely used AMS-PLL architecture due to its simplicity and robustness;2)a summary of the design issues of the basic CPPLL architecture;3)a systematic introduction of the techniques for the performance enhancement of the CPPLL;4)a brief overview of ultra-low-jitter AMS-PLL architectures which can achieve lower jitter(<100 fs)with lower power consumption compared with the CPPLL,including the injection-locked PLL(ILPLL),subsampling(SSPLL)and sampling PLL(SPLL);5)a discussion about the consideration of the AMS-PLL architecture selection,which could help designers meet their performance requirements.

Design of improved CMOS phase-frequency detector and charge-pump for phase-locked loop

Two essential blocks for the PLLs based on CP, a phase-frequency detector （PFD） and an improved current steering charge-pump （CP）, are developed. The mechanisms for widening the phase error detection range and eliminating the dead zone are analyzed and applied in our design to optimize the proposed PFD. To obtain excellent current matching and minimum current variation over a wide output voltage range, an improved structure for the proposed CP is developed by fully utilizing many additional sub-circuits. Implemented in a standard 90-nm CMOS process, the proposed PFD achieves a phase error detection range from -354° to 354° and the improved CP demonstrates a current mismatch of less than 1.1% and a pump-current variation of 4% across the output voltage, swinging from 0.2 to 1.1 V, and the power consumption is 1.3 mW under a 1.2-V supply.