Optimization of Control Loops and Operating Parameters for Three-Phase Separators Used in Oilfield Central Processing Facilities

In this study,the Stokes formula is used to analyze the separation effect of three-phase separators used in a Oilfield Central Processing Facility.The considered main influencing factors include(but are not limited to)the typical size of oil and water droplets,the residence time and temperature of fluid and the dosage of demulsifier.Using the“Specification for Oil and Gas Separators”as a basis,the control loops and operating parameters of each separator are optimized Considering the Halfaya Oilfield as a testbed,it is shown that the proposed approach can lead to good results in the production stage.

An improved arctangent algorithm based on phase-locked loop for heterodyne detection system

We present an ameliorated arctangent algorithm based on phase-locked loop for digital Doppler signal processing,utilized within the heterodyne detection system. We define the error gain factor given by the approximation of Taylor expansion by means of a comparison of the measured values and true values. Exact expressions are derived for the amplitude error of two in-phase & quadrature signals and the frequency error of the acousto-optic modulator. Numerical simulation results and experimental results make it clear that the dynamic instability of the intermediate frequency signals leads to cumulative errors, which will spiral upward. An improved arctangent algorithm for the heterodyne detection is proposed to eliminate the cumulative errors and harmonic components. Depending on the narrow-band filter, our experiments were performed to realize the detectable displacement of 20 nm at a detection distance of 20 m. The aim of this paper is the demonstration of the optimized arctangent algorithm as a powerful approach to the demodulation algorithm, which will advance the signal-to-noise ratio and measurement accuracy of the heterodyne detection system.

A novel high precision Doppler frequency estimation method based on the third-order phase-locked loop

In deep space exploration,many engineering and scientific requirements require the accuracy of the measured Doppler frequency to be as high as possible.In our paper,we analyze the possible frequency measurement points of the third-order phase-locked loop(PLL)and find a new Doppler measurement strategy.Based on this finding,a Doppler frequency measurement algorithm with significantly higher measurement accuracy is obtained.In the actual data processing,compared with the existing engineering software,the accuracy of frequency of 1 second integration is about 5.5 times higher when using the new algorithm.The improved algorithm is simple and easy to implement.This improvement can be easily combined with other improvement methods of PLL,so that the performance of PLL can be further improved.

Design of radiation hard phase-locked loop at 2.5 GHz using SOS-CMOS

A radiation hard phase-locked loop （PLL） is designed at 2.5 GHz using silicon on sapphire complementary metal-oxide-semiconductor process. Radiation hardness is achieved through improving circuit design without sacrificing real estate. Stability is guaranteed by a fully self-bias architecture. The lock time of PLL is minimized by maximizing the loop bandwidth. Frequency tuning range of voltage controlled oscillator is significantly enhanced by a novel load configuration. In addition, multiple bias stages, asynchronous frequency divider, and silicon on sapphire process jointly make the proposed PLL more radiation hard. Layout of this PLL is simulated by Cadence Spectre RF under both single event effect and total induced dose effect. Simulation results demonstrate excellent stability, lock time 〈 600 ns, frequency tuning range [1.57 GHz, 3.46 GHz], and jitter 〈 12 ps. Through comparison with PLLs in literatures, the PLL is especially superior in terms of lock time and frequency tuning range performances.

Hybrid phase-locked loop with fast locking time and low spur in a 0.18-μm CMOS process

We propose a novel hybrid phase-locked loop （PLL） architecture for overcoming the trade-off between fast locking time and low spur. To reduce the settling time and meanwhile suppress the reference spurs, we employ a wide-band single-path PLL and a narrow-band dual-path PLL in a transient state and a steady state, respectively, by changing the loop bandwidth according to the gain of voltage controlled oscillator （VCO） and the resister of the loop filter. The hybrid PLL is implemented in a 0.18-μm complementary metal oxide semiconductor （CMOS） process with a total die area of 1.4×0.46 mm2. The measured results exhibit a reference spur level of lower than -73 dB with a reference frequency of 10 MHz and a settling time of 20 μs with 40 MHz frequency jump at 2 GHz. The total power consumption of the hybrid PLL is less than 27 mW with a supply voltage of 1.8 V.

A Digital Phase Locked Loop Speed Control of Three Phase Induction Motor Drive: Performances Analysis

This paper deals with performance analysis and implementation of a three phase inverter fed induction motor (IM) drive system. The closed loop control scheme of the drive utilizes the Digital Phase Locked Loop (DPLL). The DPLL is safely implemented all around the well known integrated circuit DPLL 4046. An ex-perimental verification is carried out on one kw scalar controlled IM system drives for a wide range of speeds and loads appliance. This presents a simple and high performance solution for industrial applications.

A LOW POWER TIME-TO-DIGITAL CONVERTER FOR ALL-DIGITAL PHASE-LOCKED LOOP

Time-to-Digital Converter (TDC) is a key block used as the phase/frequency detector in an All-Digital Phase-Locked Loop (ADPLL). Usually, it occupies a large proportion of ADPLL's total power consumption up to about 30% to 40%. In this paper, the detailed power consumption of different components in the TDC is analyzed. A Power Management Block (PMB) is presented for the TDC to reduce its power consumption. A 24-bits TDC core with the proposed PMB is implemented in HJTC 0.18 μm CMOS technology. Simulation results show that up to 84% power reduction is achieved using our proposed technique.

Multi-Order Intermittent Chaotic Synchronization of Closed Phase Locked Loop

For the model of a Closed Phase Locked Loop (CPLL) communication System consists of both the transmission and receiver ends. This model is considered to be in a multi-order intermittent chaotic state. The chaotic signals are then synchronized along side with our system. This chaotic synchronization will be demonstrated and furthermore, a modulation will be formed to examine the system if it will perfectly reconstruct or not. Finally we will demonstrate the synchronization conditions of the system.

Low phase noise millimeter wave monolithic integrated phase locked-loop

A Monolithic integrated phase locked-loop （PLL） with a low phase noise is proposed in this paper. Several techniques are utilized to improve the performance of the PLL which works at the milli- meter-wave band. The on-chip high-Q eoplanar waveguides （CPWs） are utilized in the resonant tank and the differential current amplifier with a resonator is used to realize the VCO. In the output buffer circuit, several stages of cascaded source-followers connect and differential amplifiers are adopted to improve the driving capability of the PLL＇ s output signals. An improved analog multiplier topology is also used in the PD circuit to improve the gain of the PD. The proposed PLL is realized with a 0.2p, m GaAs pseudomorphie high electron mobility transistor （PHEMT） process. At 10 kHz offset from the center frequency, the measured output phase noise of the PLL output is only -88.83dBc/Hz. The circuit exhibits a low root mean sauare （RMS） litter of 1.68Ds.

THE DESIGN OF AN ALL-DIGITAL PHASE-LOCKED LOOP WITH LOW JITTER BASED ON ISF ANALYSIS

A low jitter All-Digital Phase-Locked Loop （ADPLL） used as a clock generator is designed. The Digital-Controlled Oscillator （DCO） for this ADPLL is a seven-stage ring oscillator with the delay of each stage changeable. Based on the Impulse Sensitivity Function （ISF） analysis, an effective way is proposed to reduce the ADPLL＇s jitter by the careful design of the sizes of the inverters used in the DCO with a simple architecture other than a complex one. The ADPLL is implemented in a 0.18μm CMOS process with 1.SV supply voltage, occupies 0.046mm^2 of on-chip area. According to the measured results, the ADPLL can operate from 108MHz to 304MHz, and the peak-to-peak jitter is 139ps when the DCO＇s output frequency is 188MHz.

Novel Control Strategy for Multi-Level Active Power Filter without Phase-Locked-Loop

Active power filter (APF) using novel virtual line-flux-linkage oriented control strategy can not only realizes no phase-locked-loop (PLL) control, but also achieves a good inhibitory effect to interfere. However, there are some problems in the conventional method, such as the error of amplitude, the shift of phase angle and the non-determinacy of initial oriented angle. In this paper, two one-order low-pass filters are adopted instead of the pure integrator in the virtual line-flux-linkage observer, which can steady the phase and amplitude. Furthermore, an original scheme of harmonics detection under the rotating coordinate is advanced based on the simplified space vector pulse width modulation (SVPWM) strategy. Meanwhile, by using the new SVPWM algorithm, the voltage space vector diagram of the three-level inverter can be simplified and applied into that of two-level inverter, and this makes the control for Neutral Point potential easier.

Error Correction Circuit for Single-Event Hardening of Delay Locked Loops

In scaled CMOS processes, the single-event effects generate missing output pulses in Delay-Locked Loop (DLL). Due to its effective sequence detection of the missing pulses in the proposed Error Correction Circuit (ECC) and its portability to be applied to any DLL type, the ECC mitigates the impact of single-event effects and completes its operation with less design complexity without any concern about losing the information. The ECC has been implemented in 180 nm CMOS process and measured the accuracy of mitigation on simulations at LETs up to 100 MeV-cm2/mg. The robustness and portability of the mitigation technique are validated through the results obtained by implementing proposed ECC in XilinxArtix 7 FPGA.

Phase-Locked Loop Based Cancellation of ECG Power Line Interference

Power line(PL)interference is one significant artifact in electrocardiography(ECG)that needs to be reduced to ensure accurate recording of cardiac signals.Because PL interference is non-stationary and has varying frequency,phase,and amplitude in ECG measurement,adaptive techniques are often necessary to track and cancel the interference.In this paper we present a phase-locked loop(PLL)-based adaptive filter to cancel PL interference.The PLL obtains the reference signal that is fed into the adaptive filter to remove the PL interference at the central frequency of 50 Hz.It is found that the technique can effectively cancel PL interference in real ECG signals and,when compared with some existing techniques such as least mean squares(LMS)adaptive filter,the new technique produces better results in terms of signal-to-interference ratio(SIR).

A Static Phase Offset Reduction Technique for Multiplying Delay-Locked Loop

Static phase offset (SPO) in conventional multiplying delay-locked loops (MDLLs) dramatically degrades the deterministic jitter performance. To overcome the issue, this paper presents a new SPO reduction technique for MDLLs. The technique is based on the observation that the SPO of MDLL is mainly caused by the non-idealities on charge pump (e.g. sink and source current mismatch), and control line (e.g. gate leakage of loop filter and voltage controlled delay line (VCDL) control circuit). With a high gain stage inserting between phase detector/phase frequency detector (PD/PFD) and charge pump, the equivalent SPO has been decreased by a factor equal to the gain of the gain stage. The effectiveness of the proposed technique is validated by a Simulink model of MDLL. The equivalent SPO is measured by the power level of reference spur.

Dynamic Free-Spectral-Range Measurement for Fiber Resonator Based on Digital-Heterodyne Optical Phase-Locked Loop

We propose a novel scheme, based on digital-heterodyne optical phase-locked loop with whole-fiber circuit, to dynamically measure the free-spectral-range of a fiber resonator. The optical phase-locked loop is established with a differential frequency-modulation module consists of a pair of acousto-optic modulators. The resonance-tracking loop is derived with the Pound-Drever-Hall technique for locking the heterodyne frequency of the OPLL on the frequency difference between adjacent resonance modes. A stable locking accuracy of about 7 × 10?9 and a dynamic locking accuracy of about 5 × 10?8 are achieved with the FSR of 8.155 MHz, indicating a bias stability of the resonator fiber optic gyro of about 0.1?/h with 10 Hz bandwidth. In addition, the thermal drift coefficient of the FSR is measured as 0.1 Hz/?C. This shows remarkable potential for realizing advanced optical measurement systems, such as the resonant fiber optic gyro, and so on.

A Synchronized Grid Integrated Three-Phase Inverter with a Renewable Source for Power Sharing

In this paper, a three-phase inverter with renewable source input is integrated into a grid in synchronization for power sharing by load. In previous topologies, the DC source connected inverter is not synchronized to the grid which causes harmonics and voltage distortions damaging the load and the source. In order to ensure power sharing by the load from the inverter and the grid, the inverter needs to be operated in synchronization to the grid with the same voltage mag-nitude, frequency and phase as that of the grid voltage. In this paper, the com-plete power from the load is shared by the three-phase grid and the three-phase inverter module reducing the consumption from the conventional grid. This is achieved using the PLL for the reference angular frequency generation with feedback from grid voltage and is connected to the sinusoidal PWM generator. The PLL is used to generate unit vector template reference signals for the signal generator operating the six-switch inverter. The inverter and grid are inter-connected through LC filter for the reduction of harmonics. The power sharing, voltage, and current graphs with THD analysis are analyzed with the help of the MATLAB software.

Development of a Low-cost Hardware-in-the-loop Simulation System as a Test Bench for Anti-lock Braking System

Nowadays validation of anti-lock braking systems（ABS） relies mainly on a large amount of road tests.An alternative means with higher efficiency is employing the hardware-in-the-loop simulation（HILS） system to substitute part of road tests for designing,testing,and tuning electronic control units（ECUs） of ABS.Most HILS systems for ABS use expensive digital signal processor hardware and special purpose software,and some fail-safe functions with regard to wheel speeds cannot be evaluated since artificial wheel speed signals are usually provided.In this paper,a low-cost ABS HILS test bench is developed and used for validating the anti-lock braking performance and tuning control parameters of ABS controllers.Another important merit of the proposed test bench is that it can comprehensively evaluate the fail-safe functions with regard to wheel speed signals since real tone rings and sensors are integrated in the bench.A 5-DOF vehicle model with consideration of longitudinal load transfer is used to calculate tire forces,wheel speeds and vehicle speed.Each of the four real-time wheel speed signal generators consists of a servo motor plus a ring gear,which has sufficient dynamic response ability to emulate the rapid changes of the wheel speeds under strict braking conditions of very slippery roads.The simulation of braking tests under different road adhesion coefficients using the HILS test bench is run,and results show that it can evaluate the anti-lock braking performance of ABS and partly the fail-safe functions.This HILS system can also be used in such applications as durability test,benchmarking and comparison between different ECUs.The test bench developed not only has a relatively low cost,but also can be used to validate the wheel speed-related ECU design and all its fail-safe functions,and a rapid testing and proving platform with a high efficiency for research and development of the automotive ABS is therefore provided.

A sapphire fibre thermal probe based on fast Fourier transform and phase-lock loop

A sapphire fibre thermal probe with Cr^3＋ ion-doped end is developed by using the laser heated pedestal growth method. The fluorescence thermal probe offers advantages of compact structure, high performance and ability to withstand high temperature in a detection range from room temperature to 450℃. Based on the fast Fourier transform （FFT）, the fluorescence lifetime is obtained from the tangent function of phase angle of the non-zeroth terms in the FFT result. This method has advantages such as quick calculation, high accuracy and immunity to the background noise. This FFT method is compared with other traditional fitting methods, indicating that the standard deviation of the FFT method is about half of that of the Prony method and about 1/6 of that of the log-fit method. And the FFT method is immune to the background noise involved in a signal. So, the FFT method is an excellent way of processing signals. In addition, a phase-lock amplifier can effectively suppress the noise.

Hierarchy of Protein Loop-Lock Structures: A New Server for the Decomposition of a Protein Structure into a Set of Closed Loops

HoPLLS (Hierarchy of protein loop-lock structures) (http://leah.haifa.ac.il/~skogan/Apache/mydata1/main.html) is a web server that identifies closed loops-a structural basis for protein domain hierarchy. The server is based on the loop-and-lock theory for structural organisation of natural proteins. We describe this web server, the algorithms for the decomposition of a 3D protein into loops and the results of scientific investigations into a structural “alphabet” of loops and locks.

高渗透率下基于并网逆变器阻抗重塑的锁相环设计方法

针对锁相环、电网阻抗与并网逆变器相互耦合所引发的系统稳定性下降问题。首先,建立考虑电网阻抗的锁相环控制结构模型,通过分析锁相环闭环传递函数可知,电网阻抗会使锁相环系统产生右半平面闭环极点,严重影响锁相环与逆变器系统的稳定性。其次,通过分析逆变器系统输出阻抗,说明锁相环所引入的负阻抗是逆变器系统稳定裕度下降的主要原因。鉴于此,该文提出一种新型锁相环设计方法,理论分析表明,所提方法既能够保证高渗透率下锁相环具有高鲁棒性,又能够对逆变器系统输出阻抗进行重塑,有效拓宽系统对电网阻抗的适应范围。最后,通过仿真与实验验证所提新型锁相环设计方法的有效性。