A high precision time-to-digital converter based on multi-phase clock implemented within Field-Programmable-Gate-Array

In this paper, the design of a coarse-fine interpolation Time-to-Digital Converter (TDC) is implemented in an ALTERA’s Cyclone FPGA. The carry-select chain performs as the tapped delay line. The Logic Array Block (LAB) having a propagation delay of 165 ps in the chain is synthesized as delay cell. Coarse counters triggered by the global clock count the more significant bits of the time data. This clock is also fed through the delay line, and LABs create the copies. The replicas are latched by the tested event signal, and the less significant bits are encoded from the latched binary bits. Single-shot resolution of the TDC can be 60 ps. The worst Differential Nonlinearity (DNL) is about 0.2 Least Significant Bit (LSB, 165 ps in this TDC module), and the Integral Nonlinearity (INL) is 0.6 LSB. In comparison with other architectures using the synchronous global clock to sample the taps, this architecture consumed less electric power and logic cells, and is more stable.

A LOW POWER TIME-TO-DIGITAL CONVERTER FOR ALL-DIGITAL PHASE-LOCKED LOOP

Time-to-Digital Converter (TDC) is a key block used as the phase/frequency detector in an All-Digital Phase-Locked Loop (ADPLL). Usually, it occupies a large proportion of ADPLL's total power consumption up to about 30% to 40%. In this paper, the detailed power consumption of different components in the TDC is analyzed. A Power Management Block (PMB) is presented for the TDC to reduce its power consumption. A 24-bits TDC core with the proposed PMB is implemented in HJTC 0.18 μm CMOS technology. Simulation results show that up to 84% power reduction is achieved using our proposed technique.

Novel Optical Analog-To-Digital Converter Based on Optical Time Division Multiplexing

A novel optical analog-to-digital converter based on optical time division multiplexing(OTDM) is described which uses electrooptic sampling and time-demultiplexing together with multiple electronic analog-to-digital converter(ADC). Compared with the previous scheme, the time-division multiplexer and the time-division demultiplexer are applied in the optical analog-to-digital converter(OADC) at the same time, the design of the OADC is simplified and the performance of the OADC based on time-division demultiplexer is improved. A core optical part of the system is demonstrated with a sample rate of 10 Gs/s. The signals in three channels are demultiplexed from the optical pulses.The result proves our scheme is feasible.

Single-Stage Vernier Time-to-Digital Converter with Sub-Gate Delay Time Resolution

This paperpresents a single-stage Vernier Time-to-Digital Converter (VTDC) that utilizes the dynamic-logic phase detector. The zero dead-zone characteristic of this phase detector allows for the single-stage VTDC to deliver sub-gate delay time resolution. The single-stage VTDC has been designed in 0.13μm CMOS technology. The simulation results demonstrate a linear input-output characteristic for input dynamic range from 0 to 1.6ns with a time resolution of 25ps.

PULSE SHRINKING TIME-TO-DIGITAL CONVERTER FOR UWB APPLICATION

A kind of architecture of Time-to-Digital Converter(TDC) for Ultra-WideBand(UWB) application is presented. The proposed TDC is based on pulse shrinking, and implemented in a Field Programmable Gate Array(FPGA) device. The pulse shrinking is realized in a loop containing two Programmable Delay Lines(PDLs) or a two-channel PDL. One line(channel) delays the rising edge and the other line(channel) delays the falling edge of a circulating pulse. Delay resolution of PDL is converted into a digital output code under known conditions of pulse width. This delay resolution measurement mechanism is different from the conventional time interval measurement mechanism based on pulse shrinking of conversion of unknown pulse width into a digital output code. This mechanism automatically avoids the influence of unwanted pulse shrinking by any circuit element apart from the lines. The achieved relative errors for four PDLs are within 0.80%–1.60%.

A 5-bit time to digital converter using time to voltage conversion and integrating techniques for agricultural products analysis by Raman spectroscopy

Time to digital converter(TDC)is a key block for time-gated single photon avalanche diode(SPAD)arrays for Raman spectroscopy that applicable in the agricultural products and food analysis.In this paper a new dual slope time to digital converter that employs the time to voltage conversion and integrating techniques for digitizing the time interval input signals is presented.The reference clock frequency of the TDC is 100 MHz and the input range is theoretically unlimited.The proposed converter features high accuracy,very small average error and high linear range.Also this converter has some advantages such as low circuit complexity,low power consumption and low sensitive to the temperature,power supply and process changes(PVT)compared with the time to digital converters that used preceding conversion techniques.The proposed converter uses an indirect time to digital conversion method.Therefore,our converter has the appropriate linearity without extra elements.In order to evaluate the proposed idea,an integrating time to digital converter is designed in 0.18 lm CMOS technology and was simulated by Hspice.Comparison of the theoretical and simulation results confirms the proposed TDC operation;therefore,the proposed converter is very convenient for applications which have average speed and low variations in the signal amplitude such as biomedical signals.

Readout electronics of a prototype time-of-flight ion composition analyzer for space plasma

Readout electronics is developed for a prototype time-of-flight(TOF) ion composition spectrometer for in situ measurement of the mass/charge distributions of major ion species from 200 to 100 ke V/e in space plasma.By utilizing a constant fraction discriminator(CFD) and time-to-digital converter(TDC), challenging dynamic range measurements were performed with high time resolution and event rates. CFD was employed to discriminate the TOF signals from the micro-channel plate and channel electron multipliers. TDC based on the combination of counter and OR-gate delay chain was designed in a highreliability flash field programmable gate array. Owing to the non-uniformity of the delay chain, a correction algorithm based on integral nonlinearity compensation was implemented to reduce the time uncertainty. The test results showed that the electronics achieved a low timingerror of < 200 ps in the input range from 35 to 500 m V for the CFD, and a time resolution of ～550 ps with time uncertainty < 180 ps after correction and a time range of6.4 ls for the TDC. The TOF spectrum from an electron beam experiment of the impacting N_2 gas further indicated the good performance of this readout electronic.

A Timing Skew Calibration Scheme in Time-Interleaved ADC

This paper proposes a digital background calibration scheme for timing skew in time-interleaved analog-to-digital converters (TIADCs). It detects the relevant timing error by subtracting the output difference with the sum of the first derivative of the digital output. The least-mean-square (LMS) loop is exploited to compensate the timing skew. Since the calibration scheme depends on the digital output, all timing skew sources can be calibrated and the main ADC is maintained. The proposed scheme is effective within the entire frequency range of 0 ? fs/2. Compared with traditional calibration schemes, the proposed approach is more feasible and consumes significantly lesser power and smaller area.

A novel trajectory prediction control for proximate time-optimal digital control DC–DC converters

The purpose of this paper is to present a novel trajectory prediction method for proximate time-optimal digital control DC-DC converters. The control method provides pre-estimations of the duty ratio in the next several switching cycles, so as to compensate the computational time delay of the control loop and increase the control loop bandwidth, thereby improving the response speed. The experiment results show that the fastest transient response time of the digital DC-DC with the proposed prediction is about 8/μs when the load current changes from 0.6 to 0.1A.

Development of readout electronics for bunch arrival-time monitor system at SXFEL

A bunch arrival-time monitor(BAM) system,based on electro-optical intensity modulation scheme, is under study at Shanghai Soft X-ray Free Electron Laser.The aim of the study is to achieve high-precision time measurement for minimizing bunch fluctuations. A readout electronics is developed to fulfill the requirements of the BAM system. The readout electronics is mainly composed of a signal conditioning circuit, field-programmable gate array(FPGA), mezzanine card(FMC150), and powerful FPGA carrier board. The signal conditioning circuit converts the laser pulses into electrical pulse signals using a photodiode. Thereafter, it performs splitting and low-noise amplification to achieve the best voltage sampling performance of the dual-channel analog-to-digital converter(ADC) in FMC150. The FMC150 ADC daughter card includes a 14-bit 250 Msps dual-channel high-speed ADC,a clock configuration, and a management module. The powerful FPGA carrier board is a commercial high-performance Xilinx Kintex-7 FPGA evaluation board. To achieve clock and data alignment for ADC data capture at a high sampling rate, we used ISERDES, IDELAY, and dedicated carry-in resources in the Kintex-7 FPGA. This paper presents a detailed development of the readout electronics in the BAM system and its performance.

相控-延时链混合架构时间数字转换器

高精度时间间隔测量过程中,为兼顾测量分辨和精度的同时,简化校准过程,提出一种混合架构的时间数字转换器(TDC)设计方法。该方法将相控时钟架构与抽头延时链(TDL)架构结合,利用不同相位的时钟对抽头延时链实现并行采样,一次测量过程中可以得到多个测量值,最后利用多个测量值的均值表示测量结果。该方法在Kintex-7 FPGA上进行实验测试,结果表明在进行简单校准的情况下,仍然可以保持较高的测量分辨率和精度,从而证明提出方法的有效性与可行性。

A time and charge measurement board for muon tomography of high-Z materials

In this paper, a versatile time and charge measurement(MQT) board for muon tomography is described in detail. For time measurement, the general-purpose timeto-digital converter(TDC) chip TDC-GP2 is employed,while for charge measurement, digitization plus numerical integration in field programmable gate array is employed.Electronic tests demonstrate that the total 32 channels of two MQT boards have a time resolution of superior than100 ps, with excellent linearity for time and charge measurement.

Design of a 10 bit high resolution,high speed time-to-digital converter using a two-step pulse-train time amplifier

A high resolution and fast conversion rate time-to-digital converter （TDC） design based on time amplifier （TA） is proposed. The pulse-train TA employs a two-step scheme. The input time interval is first amplified by a N-times TA and the effective time is extracted in pulse-train using a time-register. Then the resulted interval is further amplified by the other pulse-train amplifier to obtain the final result. The two-step TA can thus achieve large gain that is critical for high resolution TDC. Simulation results in 1.2 V, 65 nm technology showed that for a 10 bit TDC, a resolution of 0. 8 ps and a conversion rate of 150 MS/s are achieved while consuming 2. 1 mW power consumption.

An 8-bit 100-MS/s digital-to-skew converter embedded switch with a 200-ps range for time-interleaved sampling

A sampling switch with an embedded digital-to-skew converter(DSC) is presented.The proposed switch eliminates time-interleaved ADCs' skews by adjusting the boosted voltage.A similar bridged capacitors' charge sharing structure is used to minimize the area.The circuit is fabricated in a 0.18μm CMOS process and achieves sub-1 ps resolution and 200 ps timing range at a rate of 100 MS/s.The power consumption is 430μW at maximum.The measurement result also includes a 2-channel 14-bit 100 MS/s time-interleaved ADCs(TI-ADCs) with the proposed DSC switch's demonstration.This scheme is widely applicable for the clock skew and aperture error calibration demanded in TI-ADCs and SHA-less ADCs.

A multi-path gated ring oscillator based time-to-digital converter in 65 nm CMOS technology

A gated ring oscillator(GRO) based time-to-digital converter(TDC) is presented.To enhance the resolution of the TDC,a multi-path structure for the GRO is used to achieve a higher oscillation frequency and an input stage is also presented to equivalently amplify the input time difference with a gain of 2.The GRO based TDC circuit is fabricated in TSMC 65 nm CMOS technology and the core area is about 0.02 mm^2.According to the measurement results,the effective resolution of this circuit is better than 4.22 ps under a 50 MHz clock frequency. With a 1 ns input range,the maximum clock frequency of this circuit is larger than 200 MHz.Under a 1 V power supply,with a 200-800 ps input time difference,the measured power consumption is 1.24 to 1.72 mW at 50 MHz clock frequency and 1.73 to 2.20 mW at 200 MHz clock frequency.

基于时钟抖动流水线结构的高效率真随机数发生器

现代加密系统对密钥随机性的需求不断增加。使用时序抖动、热噪声、亚稳态等作为熵源的真随机数发生器,因其可以提供高质量的随机性成为该领域的研究热点。因此,提出一种可配置、轻量级、高效率的真随机数发生器。该发生器使用基于随机数学模型的设计方法,由差分构架的两级时钟抖动流水线组成。第一级流水线中两个环形振荡器在规定时间内累积抖动,第二级流水线利用近似相同的两个环形振荡器的微小周期差构建时间数字转换器,对第一级输出的高斯抖动进行量化,通过数字化模块输出随机比特。在时间数字转换器运行过程中,第一级流水线已经重新启动累积下一个阶段的抖动,减少了空闲时间,提高了真随机数的质量和效率。在Xilinx Atrix-7平台进行了验证,该结构的硬件资源仅消耗了25个LUTs和13个DFFs,获得高达32.55 Mb/s的吞吐量。

光子计数激光雷达时间-数字转换系统

时间测量系统在激光雷达中主要用于激光脉冲飞行时间的测量,其性能直接影响着激光雷达的各项指标.基于FPGA设计了一种应用于光子计数激光雷达的时间-数字转换(Time-to-Digital Converter,TDC)系统,利用延迟线内插在FPGA内部实现了高精度的时间测量,通过实验分析,研究了TDC系统的性能及其应用于光子计数激光雷达后的效果.实验结果表明,TDC系统的时间分辨率达到29 ps,测时精度37 ps,能够实现9通道的高精度事件计时功能,用于光子计数激光雷达后,整个激光雷达系统的测时精度为421 ps,达到6.3 cm的距离测量精度,能够实现高精度高分辨率的激光三维成像.

线性碲镉汞APD的高速焦平面读出电路研究

设计了一款针对线性模式碲镉汞APD的高速成像读出电路。像元内基于三级推挽放大器级联的电阻反馈跨导放大器(RTIA),实现了光电流的实时线性转换,并利用工作于亚阈值区的MOS管作为反馈电阻实现跨阻增益可调;利用电容补偿法对RTIA的相位裕度进行优化,解决了低增益下的输出振荡现象。结果显示,像元内RTIA跨阻增益可调范围达100~140 dB,增益带宽积可达10^(14)数量级,像元电路输出延时低于1.8 ns。设计了像素外的飞行时间测量电路,采用两段式时间数字转换器分别进行飞行时间的大范围粗量化和高精度细量化,测量范围可达1530 m,测量精度为106.5 cm,线性度高于99.99%。

基于高速ADC的数字双混频时差测量系统

使用双混频时差法进行时间和频率测量时,模拟部分引入的噪声会干扰信号过零点的判断,降低测量精度,而使用数字信号处理技术后不再需要判断过零点,量化噪声成为系统内的主要噪声来源,可以通过数字滤波器对其进行抑制。同时有利于设计结构紧凑的系统,更易于小型化,测量速度也可以进行灵活配置。通过引入高速模数转换器、数控振荡器、低通抽取滤波器、数字鉴相器等,设计了数字双混频时差测量系统,并研制了4通道的原理样机。测试结果表明,当频率源为10 MHz的信号时,原理样机中属于同片ADC(analog-to-digital converter)的两个通道间的本底噪声约为5×10^(-14)@1 s,属于不同片ADC的两个通道间的本底噪声约为8×10^(-14)@1 s,满足原子振荡器的测量要求。并以主动型氢钟VCH-1003M为参考,使用原理样机分别对Microchip的5071A铯原子钟和SRS的FS725铷原子钟的稳定度进行测量,测量结果与Microchip的相噪分析仪53100A和5120A无显著差异。

基于时间-数字转换的精密时差测量系统设计

精密时差测量在激光测距、无源时差定位、航空遥控遥测等领域有着广泛的应用。提出时间-数字转换技术的时差测量方法,设计一种基于TDC-GP1的高精度时差测量系统,并介绍测量系统设计方法和软、硬件实现原理。所设计的系统具有配置灵活、可靠性高、功耗低等优点。通过对实际测量数据的分析表明,系统可以实现纳秒级的时间间隔测量。