A low power 12-bit 200-kS/s SAR ADC is proposed.This features a differential time domain comparator whose offset is cancelled by using a charge pump and a phase frequency detector instead of the preamplifiers usually ...A low power 12-bit 200-kS/s SAR ADC is proposed.This features a differential time domain comparator whose offset is cancelled by using a charge pump and a phase frequency detector instead of the preamplifiers usually needed in a high resolution comparator.The proposed ADC is manufactured in 0.18-μm CMOS technology and the measured SNR and SNDR are 62.5 dB and 59.3 dB,respectively,with a power consumption of 72μW at a 200-kS/s sampling rate.The device operates with a 1.8-V power supply and achieves a FOM of 477 fJ/conversion-step.展开更多
This paper presents a 6-bit 20-MS/s high spurious-free dynamic range（SFDR） and low power successive approximation register analog to digital converter（SAR ADC） for the radio-frequency（RF） transceiver frontend, e...This paper presents a 6-bit 20-MS/s high spurious-free dynamic range（SFDR） and low power successive approximation register analog to digital converter（SAR ADC） for the radio-frequency（RF） transceiver frontend, especially for wireless sensor network（WSN） applications.This ADC adopts the modified common-centroid symmetry layout and the successive approximation register reset circuit to improve the linearity and dynamic range. Prototyped in a 0.18-μm 1P6M CMOS technology,the ADC performs a peak SFDR of 55.32 dB and effective number of bits（ENOB） of 5.1 bit for 10 MS/s.At the sample rate of 20 MS/s and the Nyquist input frequency,the 47.39-dB SFDR and 4.6-ENOB are achieved.The differential nonlinearity（DNL） is less than 0.83 LSB and the integral nonlinearity（INL） is less than 0.82 LSB.The experimental results indicate that this SAR ADC consumes a total of 522μW power and occupies 0.98 mm^2.展开更多
This study presents a CMOS receiver chip realized in 0.18μm standard CMOS technology and in- tended for high precision 3-D laser radar. The chip includes an adjustable gain transimpedance pre-amplifier, a post-amplif...This study presents a CMOS receiver chip realized in 0.18μm standard CMOS technology and in- tended for high precision 3-D laser radar. The chip includes an adjustable gain transimpedance pre-amplifier, a post-amplifier and two timing comparators. An additional feedback is employed in the regulated cascode tran- simpedance amplifier to decrease the input impedance, and a variable gain transimpedance amplifier controlled by digital switches and analog multiplexer is utilized to realize four gain modes, extending the input dynamic range. The measurement shows that the highest transimpedance of the channel is 50 kΩ, the uncompensated walk error is 1.44 ns in a wide linear dynamic range of 66 dB （1 ： 2000）, and the input referred noise current is 2.3 pA/√ （rms）, resulting in a very low detectable input current of 1μA with SNR = 5.展开更多
基金Project supported by the National Natural Science Foundation of China(No.60876021)the State Key Laboratory Project,China (No.MS20080203)
文摘A low power 12-bit 200-kS/s SAR ADC is proposed.This features a differential time domain comparator whose offset is cancelled by using a charge pump and a phase frequency detector instead of the preamplifiers usually needed in a high resolution comparator.The proposed ADC is manufactured in 0.18-μm CMOS technology and the measured SNR and SNDR are 62.5 dB and 59.3 dB,respectively,with a power consumption of 72μW at a 200-kS/s sampling rate.The device operates with a 1.8-V power supply and achieves a FOM of 477 fJ/conversion-step.
基金supported by the PhD Programs Foundation of the Ministry of Education of China(No.20111011315)the National Science and Technology Important Project of China(No.2010ZX03006-003-01)
文摘This paper presents a 6-bit 20-MS/s high spurious-free dynamic range（SFDR） and low power successive approximation register analog to digital converter（SAR ADC） for the radio-frequency（RF） transceiver frontend, especially for wireless sensor network（WSN） applications.This ADC adopts the modified common-centroid symmetry layout and the successive approximation register reset circuit to improve the linearity and dynamic range. Prototyped in a 0.18-μm 1P6M CMOS technology,the ADC performs a peak SFDR of 55.32 dB and effective number of bits（ENOB） of 5.1 bit for 10 MS/s.At the sample rate of 20 MS/s and the Nyquist input frequency,the 47.39-dB SFDR and 4.6-ENOB are achieved.The differential nonlinearity（DNL） is less than 0.83 LSB and the integral nonlinearity（INL） is less than 0.82 LSB.The experimental results indicate that this SAR ADC consumes a total of 522μW power and occupies 0.98 mm^2.
文摘This study presents a CMOS receiver chip realized in 0.18μm standard CMOS technology and in- tended for high precision 3-D laser radar. The chip includes an adjustable gain transimpedance pre-amplifier, a post-amplifier and two timing comparators. An additional feedback is employed in the regulated cascode tran- simpedance amplifier to decrease the input impedance, and a variable gain transimpedance amplifier controlled by digital switches and analog multiplexer is utilized to realize four gain modes, extending the input dynamic range. The measurement shows that the highest transimpedance of the channel is 50 kΩ, the uncompensated walk error is 1.44 ns in a wide linear dynamic range of 66 dB （1 ： 2000）, and the input referred noise current is 2.3 pA/√ （rms）, resulting in a very low detectable input current of 1μA with SNR = 5.
