Bias-dependent timing jitter of 1-GHz sinusoidally gated InGaAs/InP avalanche photodiode

We characterized the dependence of the timing jitter of an InGaAs/InP single-photon avalanche diode on the excess bias voltage（V（ex）） when operated in 1-GHz sinusoidally gated mode.The single-photon avalanche diode was cooled to-30 degrees Celsius.When the V（ex） is too low（0.2 V-0.8 V） or too high（3 V-4.2 V）,the timing jitter is increased with the V（ex）,particularly at high V（ex）.While at middle V（ex）（1 V-2.8 V）,the timing jitter is reduced.Measurements of the timing jitter of the same avalanche diode with pulsed gating show that this effect is likely related to the increase of both the amplitude of the V（ex） and the width of the gate-on time.For the 1-GHz sinusoidally gated detector,the best jitter of 93 ps is achieved with a photon detection efficiency of 21.4%and a dark count rate of -2.08×10 -5 per gate at the V（ex） of 2.8 V.To evaluate the whole performance of the detector,we calculated the noise equivalent power（NEP） and the afterpulse probability（P（ap））.It is found that both NEP and P（ap） increase quickly when the V（ex） is above 2.8 V.At -2.8-V V（ex）,the NEP and P（ap） are -2.06×10-（16）W/Hz-（1/2） and 7.11%,respectively.Therefore,the detector should be operated with V（ex） of 2.8 V to exploit the fast time response,low NEP and low P（ap）.

Investigation of response time of small footprint photonic crystal AND logic gate

In this paper, the response time of all-optical AND logic gate using the triangular photonic crystal lattice is investigated. The proposed logic gate consists of a photonic crystal nano-resonator formed by changing the size of the dielectric rods. The structure benefits the interference effect mechanism. The contrast ratio of the photonic crystal AND logic gate is obtained as 6 d B. In addition to simplicity, the designed nano-resonator increases the bit rate of logic gate. The delay time and footprint of logic gate are respectively 0.32 ps and 146 μm2. The proposed photonic crystal AND logic gate can operate at a bit rate of 3.12 Tbit/s。

A Maximum Time Difference Pipelined Arithmetic Unit Based on CMOS Gate Array

This paper describes a maximum time difference pipelined arithmetic chip,the 36-bit adder and subtractor based on 1.5 μm CMOS gate array The chipcan operate at 60MHz, and consumes less than 0.5Wat. The results are alsostudied, and a more precise model of delay time dmerence is proposed.