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Capacitor self-calibration technique used in time-interleaved successive approximation ADC
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作者 殷勤 戚韬 +1 位作者 吴光林 吴建辉 《Journal of Southeast University(English Edition)》 EI CAS 2006年第2期164-168,共5页
A capacitor self-calibration circuit used in a successive approximation analog-to-digital converter (SA-ADC) is presented. This capacitor self-calibration circuit can calibrate erroneous data and work with the ADC b... A capacitor self-calibration circuit used in a successive approximation analog-to-digital converter (SA-ADC) is presented. This capacitor self-calibration circuit can calibrate erroneous data and work with the ADC by adding an additional clock period. This circuit is used in a 10 bit 32 Msample/s time-interleaved SA- ADC. The chip is implemented with Chart 0. 25 μm 2. 5 V process and totally occupies an area of 1.4 mm× 1.3 mm. After calibration, the simulated signal-to-noise ratio (SNR) is 59. 586 1 dB and the spurious-free dynamic range (SFDR) is 70. 246 dB at 32 MHz. The measured signal-to-noise and distortion ratio (SINAD) is 44. 82 dB and the SFDR is 63. 760 4 dB when the ADC samples a 5.8 MHz sinusoid wave. 展开更多
关键词 capacitor self-calibration analog-to-digital converter successive approximation time-interleaved
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A Timing Skew Calibration Scheme in Time-Interleaved ADC 被引量:1
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作者 Jing Li Yang Liu +3 位作者 Hao Liu Shuangyi Wu Ning Ning Qi Yu 《Journal of Computer and Communications》 2013年第6期37-40,共4页
This paper proposes a digital background calibration scheme for timing skew in time-interleaved analog-to-digital converters (TIADCs). It detects the relevant timing error by subtracting the output difference with the... This paper proposes a digital background calibration scheme for timing skew in time-interleaved analog-to-digital converters (TIADCs). It detects the relevant timing error by subtracting the output difference with the sum of the first derivative of the digital output. The least-mean-square (LMS) loop is exploited to compensate the timing skew. Since the calibration scheme depends on the digital output, all timing skew sources can be calibrated and the main ADC is maintained. The proposed scheme is effective within the entire frequency range of 0 ? fs/2. Compared with traditional calibration schemes, the proposed approach is more feasible and consumes significantly lesser power and smaller area. 展开更多
关键词 TIMING SKEW BACKGROUND CALIBRATION time-interleaved analog-to-digital converterS
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A 14-bit 200-MS/s time-interleaved ADC with sample-time error calibration 被引量:1
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作者 张逸文 陈迟晓 +2 位作者 余北 叶凡 任俊彦 《Journal of Semiconductors》 EI CAS CSCD 2012年第10期116-121,共6页
Sample-time error between channels degrades the resolution of time-interleaved analog-to-digital converters (TIADCs).A calibration method implemented in mixed circuits with low complexity and fast convergence is pro... Sample-time error between channels degrades the resolution of time-interleaved analog-to-digital converters (TIADCs).A calibration method implemented in mixed circuits with low complexity and fast convergence is proposed in this paper.The algorithm for detecting sample-time error is based on correlation and widely applied to wide-sense stationary input signals.The detected sample-time error is corrected by a voltage-controlled sampling switch.The experimental result of a 2-channel 200-MS/s 14-bit TIADC shows that the signal-to-noise and distortion ratio improves by 19.1 dB,and the spurious-free dynamic range improves by 34.6 dB for a 70.12-MHz input after calibration.The calibration convergence time is about 20000 sampling intervals. 展开更多
关键词 sample-time error analog-to-digital converter CORRELATION CALIBRATION time-interleaved
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A low power time-interleaved 10-bit 250-MSPS charge domain pipelined ADC for IF sampling
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作者 陈珍海 钱宏文 +2 位作者 黄嵩人 张鸿 于宗光 《Journal of Semiconductors》 EI CAS CSCD 2013年第6期118-125,共8页
A 10-bit 250-MSPS two-channel time-interleaved charge-domain(CD) pipelined analog-to-digital converter (ADC) is presented.MOS bucket-brigade device(BBD) based CD pipelined architecture is used to achieve low pow... A 10-bit 250-MSPS two-channel time-interleaved charge-domain(CD) pipelined analog-to-digital converter (ADC) is presented.MOS bucket-brigade device(BBD) based CD pipelined architecture is used to achieve low power consumption.An all digital low power DLL is used to alleviate the timing mismatches and to reduce the aperture jitter.A new bootstrapped MOS switch is designed in the sample and hold circuit to enhance the IF sampling capability.The ADC achieves a spurious free dynamic range(SFDR) of 67.1 dB,signal-to-noise ratio (SNDR) of 55.1 dB for a 10.1 MHz input,and SFDR of 61.6 dB,SNDR of 52.6 dB for a 355 MHz input at full sampling rate.Differential nonlinearity(DNL) is +0.5/-0.4 LSB and integral nonlineariry(INL) is +0.8/-0.75 LSB.Fabricated in a 0.18-μm 1P6M CMOS process,the prototype 10-bit pipelined ADC occupies 1.8×1.3 mm2 of active die area,and consumes only 68 mW at 1.8 V supply. 展开更多
关键词 time-interleaved pipelined analog-to-digital converter charge domain low power bootstrapped sampling switch delay locked loop
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