This paper proposes a digital background calibration scheme for timing skew in time-interleaved analog-to-digital converters (TIADCs). It detects the relevant timing error by subtracting the output difference with the...This paper proposes a digital background calibration scheme for timing skew in time-interleaved analog-to-digital converters (TIADCs). It detects the relevant timing error by subtracting the output difference with the sum of the first derivative of the digital output. The least-mean-square (LMS) loop is exploited to compensate the timing skew. Since the calibration scheme depends on the digital output, all timing skew sources can be calibrated and the main ADC is maintained. The proposed scheme is effective within the entire frequency range of 0 ? fs/2. Compared with traditional calibration schemes, the proposed approach is more feasible and consumes significantly lesser power and smaller area.展开更多
Sample-time error between channels degrades the resolution of time-interleaved analog-to-digital converters （TIADCs）.A calibration method implemented in mixed circuits with low complexity and fast convergence is pro...Sample-time error between channels degrades the resolution of time-interleaved analog-to-digital converters （TIADCs）.A calibration method implemented in mixed circuits with low complexity and fast convergence is proposed in this paper.The algorithm for detecting sample-time error is based on correlation and widely applied to wide-sense stationary input signals.The detected sample-time error is corrected by a voltage-controlled sampling switch.The experimental result of a 2-channel 200-MS/s 14-bit TIADC shows that the signal-to-noise and distortion ratio improves by 19.1 dB,and the spurious-free dynamic range improves by 34.6 dB for a 70.12-MHz input after calibration.The calibration convergence time is about 20000 sampling intervals.展开更多
A 10-bit 250-MSPS two-channel time-interleaved charge-domain（CD） pipelined analog-to-digital converter （ADC） is presented.MOS bucket-brigade device（BBD） based CD pipelined architecture is used to achieve low pow...A 10-bit 250-MSPS two-channel time-interleaved charge-domain（CD） pipelined analog-to-digital converter （ADC） is presented.MOS bucket-brigade device（BBD） based CD pipelined architecture is used to achieve low power consumption.An all digital low power DLL is used to alleviate the timing mismatches and to reduce the aperture jitter.A new bootstrapped MOS switch is designed in the sample and hold circuit to enhance the IF sampling capability.The ADC achieves a spurious free dynamic range（SFDR） of 67.1 dB,signal-to-noise ratio （SNDR） of 55.1 dB for a 10.1 MHz input,and SFDR of 61.6 dB,SNDR of 52.6 dB for a 355 MHz input at full sampling rate.Differential nonlinearity（DNL） is ＋0.5/-0.4 LSB and integral nonlineariry（INL） is ＋0.8/-0.75 LSB.Fabricated in a 0.18-μm 1P6M CMOS process,the prototype 10-bit pipelined ADC occupies 1.8×1.3 mm2 of active die area,and consumes only 68 mW at 1.8 V supply.展开更多
文摘This paper proposes a digital background calibration scheme for timing skew in time-interleaved analog-to-digital converters (TIADCs). It detects the relevant timing error by subtracting the output difference with the sum of the first derivative of the digital output. The least-mean-square (LMS) loop is exploited to compensate the timing skew. Since the calibration scheme depends on the digital output, all timing skew sources can be calibrated and the main ADC is maintained. The proposed scheme is effective within the entire frequency range of 0 ? fs/2. Compared with traditional calibration schemes, the proposed approach is more feasible and consumes significantly lesser power and smaller area.
基金supported by the National Natural Science Foundation of China(No.61006025)the Special Research Funds for Doctoral Program of Higher Education of China(No.20100071110026)
文摘Sample-time error between channels degrades the resolution of time-interleaved analog-to-digital converters （TIADCs）.A calibration method implemented in mixed circuits with low complexity and fast convergence is proposed in this paper.The algorithm for detecting sample-time error is based on correlation and widely applied to wide-sense stationary input signals.The detected sample-time error is corrected by a voltage-controlled sampling switch.The experimental result of a 2-channel 200-MS/s 14-bit TIADC shows that the signal-to-noise and distortion ratio improves by 19.1 dB,and the spurious-free dynamic range improves by 34.6 dB for a 70.12-MHz input after calibration.The calibration convergence time is about 20000 sampling intervals.
基金supported by the National Science Foundation of China(No.61106027)the 333 Talent Project of Jiangsu Province,China(No. BRA2011115)
文摘A 10-bit 250-MSPS two-channel time-interleaved charge-domain（CD） pipelined analog-to-digital converter （ADC） is presented.MOS bucket-brigade device（BBD） based CD pipelined architecture is used to achieve low power consumption.An all digital low power DLL is used to alleviate the timing mismatches and to reduce the aperture jitter.A new bootstrapped MOS switch is designed in the sample and hold circuit to enhance the IF sampling capability.The ADC achieves a spurious free dynamic range（SFDR） of 67.1 dB,signal-to-noise ratio （SNDR） of 55.1 dB for a 10.1 MHz input,and SFDR of 61.6 dB,SNDR of 52.6 dB for a 355 MHz input at full sampling rate.Differential nonlinearity（DNL） is ＋0.5/-0.4 LSB and integral nonlineariry（INL） is ＋0.8/-0.75 LSB.Fabricated in a 0.18-μm 1P6M CMOS process,the prototype 10-bit pipelined ADC occupies 1.8×1.3 mm2 of active die area,and consumes only 68 mW at 1.8 V supply.
