An open-loop 20 GSps track-and-hold amplifier （THA） using fully-differential architecture to mitigate common-mode noise and suppress even-order harmonics is presented. CMOS switch and dummy switches are adopted to a...An open-loop 20 GSps track-and-hold amplifier （THA） using fully-differential architecture to mitigate common-mode noise and suppress even-order harmonics is presented. CMOS switch and dummy switches are adopted to achieve high speed and good linearity. A cross-coupled pair is used in the input buffer to suppress the charge injection and clock feedthrough. Both the input and output buffers use an active inductor load to achieve high signal bandwidth. The THA is realized with 0.18/zm SiGe BiCMOS technology using only CMOS devices at a 1.8 V voltage supply and with a core area of 0.024 mme. The measurement results show that the SFDR is 32.4 dB with a 4 GHz sine wave input at a 20 GSps sampling rate, and the third harmonic distortion is -48 dBc. The effective resolution bandwidth of the THA is 12 GHz and the figure of merit is only 0.028 mW/GHz.展开更多
基金supported by the PhD Programs Foundation of Ministry of Education of China(No.2009009211001)the Important National Science&Technology Specific Projects(No.2010ZX03006-003-02)
文摘An open-loop 20 GSps track-and-hold amplifier （THA） using fully-differential architecture to mitigate common-mode noise and suppress even-order harmonics is presented. CMOS switch and dummy switches are adopted to achieve high speed and good linearity. A cross-coupled pair is used in the input buffer to suppress the charge injection and clock feedthrough. Both the input and output buffers use an active inductor load to achieve high signal bandwidth. The THA is realized with 0.18/zm SiGe BiCMOS technology using only CMOS devices at a 1.8 V voltage supply and with a core area of 0.024 mme. The measurement results show that the SFDR is 32.4 dB with a 4 GHz sine wave input at a 20 GSps sampling rate, and the third harmonic distortion is -48 dBc. The effective resolution bandwidth of the THA is 12 GHz and the figure of merit is only 0.028 mW/GHz.
文摘基于0.7μm、ft=280 GHz的InP HBT工艺设计了一种双开关宽带超高速采样保持电路。芯片面积1.5 mm×1.8 mm,总功耗小于2.1 W。仿真结果表明,电路可以在5 GS/s采样速率下正常工作。当采样速率分别为5 GS/s和1 GS/s时,在输入信号功率为4 d Bm的情况下,采样带宽分别为16 GHz和20 GHz;在输入信号功率为4 d Bm且其频率小于5 GHz的情况下,电路的SFDR分别不低于43 d Bc和50 d Bc。
