A 2.4GHz CMOS Monolithic Transceiver Front-End for IEEE 802.11b Wireless LAN Applications

A 2. 4GHz CMOS monolithic transceiver front-end for IEEE 802. llb wireless LAN applications is presented. The receiver and transmitter are both of superheterodyne structure for good system performance. The frontend consists of five blocks., low noise amplifier,down-converter, up-converter, pre-amplifier, and LO buffer. Their input/output impedance are all on-chip matched to 50 Ω except the down-converter which has open-drain outputs. The transceiver RF front-end has been implemented in a 0. 18μm CMOS process. When the LNA and the down-converter are directly connected, the measured noise figure is 5.2dB, the measured available power gain 12. 5dB, the input l dB compression point --18dBm,and the third-order input intercept point --7dBm. The receiver front-end draws 13.6mA currents from the 1.8V power supply. When the up-converter and pre-amplifier are directly connected, the measured noise figure is 12.4dB, the power gain is 23. 8dB, the output ldB compression point is 1.5dBm, and the third-order output intercept point is 16dBm. The transmitter consumes 27.6mA current from the 1.8V power supply.

A 28/56 Gb/s NRZ/PAM-4 dual-mode transceiver with 1/4 rate reconfigurable 4-tap FFE and half-rate slicer in a 28-nm CMOS

A 28/56 Gb/s NRZ/PAM-4 dual-mode transceiver(TRx)designed in a 28-nm complementary metal-oxide-semiconduc-tor(CMOS)process is presented in this article.A voltage-mode(VM)driver featuring a 4-tap reconfigurable feed-forward equal-izer(FFE)is employed in the quarter-rate transmitter(TX).The half-rate receiver(RX)incorporates a continuous-time linear equal-izer(CTLE),a 3-stage high-speed slicer with multi-clock-phase sampling,and a clock and data recovery(CDR).The experimen-tal results show that the TRx operates at a maximum speed of 56 Gb/s with chip-on board(COB)assembly.The 28 Gb/s NRZ eye diagram shows a far-end vertical eye opening of 210 mV with an output amplitude of 351 mV single-ended and the 56 Gb/s PAM-4 eye diagram exhibits far-end eye opening of 33 mV(upper-eye),31 mV(mid-eye),and 28 mV(lower-eye)with an output amplitude of 353 mV single-ended.The recovered 14 GHz clock from the RX exhibits random jitter(RJ)of 469 fs and deterministic jitter(DJ)of 8.76 ps.The 875 Mb/s de-multiplexed data features 593 ps horizontal eye opening with 32.02 ps RJ,at bit-error rate(BER)of 10-5(0.53 UI).The power dissipation of TX and RX are 125 and 181.4 mW,respectively,from a 0.9-V sup-ply.

A 256 Gb/s electronic−photonic monolithically integrated transceiver in 45 nm CMOS

With the explosive development of artificial intelligence(AI),machine learning(ML),and high-performance comput-ing(HPC),the ever-growing data movement is asking for high density interconnects with higher bandwidth(BW),lower power and lower latency[1−3].The optical I/O leverages silicon photonic(SiPh)technology to enable high-density large-scale integrated photonics.

A 24−30 GHz 8-element dual-polarized 5G FR2 phased-array transceiver IC with 20.8-dBm TX OP1dB and 4.1-dB RX NF in 65-nm CMOS

This article presents an 8-element dual-polarized phased-array transceiver(TRX)front-end IC for millimeter-wave(mm-Wave)5G new radio(NR).Power enhancement technologies for power amplifiers(PA)in mm-Wave 5G phased-array TRX are discussed.A four-stage wideband high-power class-AB PA with distributed-active-transformer(DAT)power combining and multi-stage second-harmonic traps is proposed,ensuring the mitigated amplitude-to-phase(AM-PM)distortions across wide carrier frequencies without degrading transmitting(TX)power,gain and efficiency.TX and receiving(RX)switching is achieved by a matching network co-designed on-chip T/R switch.In each TRX element,6-bit 360°phase shifting and 6-bit 31.5-dB gain tuning are respectively achieved by the digital-controlled vector-modulated phase shifter(VMPS)and differential attenuator(ATT).Fabricated in 65-nm bulk complementary metal oxide semiconductor(CMOS),the proposed TRX demonstrates the measured peak TX/RX gains of 25.5/21.3 dB,covering the 24−29.5 GHz band.The measured peak TX OP1dB and power-added efficiency(PAE)are 20.8 dBm and 21.1%,respectively.The measured minimum RX NF is 4.1 dB.The TRX achieves an output power of 11.0−12.4 dBm and error vector magnitude(EVM)of 5%with 400-MHz 5G NR FR2 OFDM 64-QAM signals across 24−29.5 GHz,covering 3GPP 5G NR FR2 operating bands of n257,n258,and n261.

Design and Analysis of Analog Front-End of Passive RFID Transponders

An analog front-end of HF passive RFID transponders compatible with ISO/IEC 18000-3 is presented.Design considerations, especially the power transmission in the RFID transponder, are analyzed. Based on these considerations,an analog front-end is presented with novel architecture, high power conversion efficiency, low voltage, low power consumption, and high performance in an environment of noise and power fluctuation. The circuit is implemented in a Chartered 0.35μm standard CMOS process. The experimental results show that the chip can satisfy the design target well.

A Novel Digital Transceiver for CT0 Standard

This paper introduces a novel digital transceiver for the cordless telephone zero （CT0） standard,which uses a digital modulation and demodulation technique to handle the signal instead of the traditional analog meth-od. In the transmitter,a fractional-N phase locked loop （PLL） is utilized to realize the continuous phase frequency shift key （CPFSK） modulation,and a 2 Ts raised cosine （2RC） shaping technique is used to reduce the occupied bandwidth. In the receiver,a novel digital method is proposed to demodulate the 2RC CPFSK signal. This chip is fabricated using an SMIC 0.35μm mixed signal CMOS process with a die size of 2mm × 2mm. With an external low noise amplifier （LNA）,the sensitivity of the chip is better than -103dBm.

Low Voltage CMOS Gilbert Mixers for Bluetooth Transceiver

Based on the analyses of the reported Gilbert mixers operating at low supply vol tage,a down-conversion mixer and an up-conversion mixer for 2.4GHz bluetooth transceiver are presented with the modified low voltage design techniques,respe ctively.Feedback and current mirror techniques suitable for low voltage operatio n are used to improve the linearity of the up-conversion mixer,and folded-casc ode output stage is adopted to optimize the noise and conversion gain of the dow n-conversion mixer operating at low voltage.Based on 0.35μm CMOS technology,s imulations are performed with 2V supply voltage.The results show that 20dBm thir d-order intercept point (IIP3),87mV output signal amplitude are achieved for up -conversion mixer with about 3mA current;while 20dB conversion gain (CG),6.5nV /Hz input-referred noise,4.4dBm IIP3 are obtained for down-conversion mixer with about 3.5mA current.

Implementation of a 6 GHz band TDD RF transceiver for the next generation mobile communication system

The development of a high performance wideband radio frequency （RF） transceiver used in the next generation mobile communication system is presented. The developed RF transceiver operates in the 6 to 6.3 GHz band and the channel bandwidth is up to 100 MHz. It operates in the time division duplex （TDD） mode and supports the multiple-input multipleoutput （MIMO） technique for the international mobile telecommunications （IMT）-advanced systems. The classical superheterodyne scheme is employed to achieve optimal performance. Design issues of the essential components such as low noise amplifier, power amplifier and local oscillators are described in detail. Measurement results show that the maximum linear output power of the RF transceiver is above 23 dBm, and the gain and noise figure of the low noise amplifier is around 24 dB and below 1 dB, respectively. Furthermore, the error vector magnitude （EVM） measurement shows that the performance of the developed RF transceiver is well beyond the requirements of the long term evolution （LTE）-advanced system. With up to 8 x 8 MIMO configuration, the RF transceiver supports more than a 1 Gbit/s data rate in field tests.

CMOS Mixers for 2.4GHz WLAN Transceivers

A down-conversion mixer and an up-conversion mixer for 2.4GHz WLAN transceivers are presented.The down-conversion mixer uses a class-AB input stage to get high linearity and to realize input impedance matching and single-ended to differential conversion.The mixers are implemented in 0.18μm CMOS process.The measured results are given to show their performance.

Design and Test of a CMOS Low Noise Amplifier in Bluetooth Transceiver

A RF low noise amplifier,integrated in a single bluetooth transceiver chip and fabricated in 0.35μm digital CMOS technology,is presented.Under the consideration of ESD protection and package,design methodology is discussed from the aspects of noise optimization,impedance match,and forward gain.At 2.05GHz,the measured S 11 is -6.4dB, S 21 is 11dB with 3dB-BW of 300MHz,and NF is about 5.3dB.It indicates that comprehensive consideration of parasitics,package model,and reasonable process is necessary for RF circuit design.

A 12-Channel,30Gb/s,0.18μm CMOS Front-End Amplifier for Parallel Optic-Fiber Receivers

This paper presents a 12-channel,30Gb/s front-end amplifier realized in standard 0.18μm CMOS technology for parallel optlc-fiber receivers. In order to overcome the problem of inadequate bandwidth caused by the large parasitical capacitor of CMOS photo-detectors,a regulated-cascode structure and noise optimization are used in the design of the transimpedance amplifier. The experimental results indicate that, with a parasitical capacitance of 2pF,a single channel is able to work at bite rates of up to 2.5Gb/s,and a clear eye diagram is obtained with a 0. 8mVpp input. Furthermore, an isolation structure combined with a p^＋ guard.ring （PGR）, an n^＋ guard-ring （NGR）,and a deep-n-well （DNW） for parallel amplifier is also presented. Taking this combined structure, the crosstalk and the substrate noise coupling have been effectively reduced. Compared with the isolation of PGR or PGR ＋ NGR,the measured results show that the isolation degree of this structure is improved by 29.2 and 8. ldB at 1GHz,and by 8. 1 and 2. 5dB at 2GHz,respectively. With a 1.8V supply,each channel of the front-end amplifier consumes a DC power of 85mW,and the total power consumption of 12 channels is about 1W.

Patent Information Analysis of Front-end Industry Chain in China's Tobacco Industry

The research performed analysis on patent applicant ranking, IPC, patent type and legal status in order to explore application and authorization of front-end industry chain dominated by planting, breeding, soil improvement and substrate culti- vation technologies. The results showed that research institutions and big tobacco enterprises play a leading role in the tobacco industry, for example, Yunnan Tobac- co Agricultural S＆T Research Institute and Guizhou Tobacco Agricultural S＆T Re- search Institute have a total of 26 patents; A01G subclass represents 58% of total patents, dominated by Yunnan Tobacco Agricultural S＆T Research Institute and Henan Agricultural University; there are only invention and practical use patents, of which invention patents represent 92%; authorized patents take up to 31% and in- valid patents represent 23%.

Analysis and Design of a Low-Cost RFID Tag Analog Front-End

A new,low-cost RFID tag analog front-end compatible with ISO 14443A and ISO 14443B is presented. By substituting conventional multi-circle antenna with single-circle antenna, the package cost of the tag is greatly reduced. Based on this exasperate antenna performance,a new rectifier with high power conversion efficiency and low turn-on voltage is presented. The circuit is implemented in an SMIC 0.18μm EEPROM process. Measurement results show that with a 120kΩ load,the power conversion efficiency reaches as high as 36%. For a sinusoidal wave with magnitude of 0. 5V, the output DC voltage reaches IV,which is high enough for RFID tags. The read distance is as far as 22cm.

A Low Noise,1.25Gb/s Front-End Amplifier for Optical Receivers

This paper presents a low noise, 1.25Gb/s and 124dBΩ front-end amplifier that is designed and fabricated in 0.25μm CMOS technology for optical communication applications. Active inductor shunt peaking technology and noise optimization are used in the design of a trans-impedance amplifier,which overcomes the problem of inadequate bandwidth caused by the large parasitical capacitor of the CMOS photodiode. Experimental results indicate that with a parasitical capacitance of 2pF,this circuit works at 1.25Gb/s. A clear eye diagram is obtained with an input optical signal of - 17dBm. With a power supply of 3.3V, the front-end amplifier consumes 122mW and provides a 660mV differential output.

Joint Transceiver Designs for Full-Duplex MIMO SWIPT Systems Based on MSE Criterion

For the simultaneous wireless information and power transfer(SWIPT), the full-duplex MIMO system can achieve simultaneous transmission of information and energy more efficiently than the half-duplex. Based on the mean-square-error(MSE) criterion, the optimization problem of joint transceiver design with transmitting power constraint and energy harvesting constraint is formulated. Next, by semidefinite relaxation(SDR) and randomization method, the SDRbased scheme is proposed. In order to reduce the complexity, the closed-form scheme is presented with some simplified measures. Robust beamforming is then studied considering the practical condition. The simulation results such as MSE versus signal-noise-ratio(SNR), MSE versus the iteration number, well prove the performance of the proposed schemes for the system model.

A 40 Gb/s SerDes Transceiver Chip with Controller and PHY in a 65 nm CMOS Technology

A 40 Gb/s full serializer and deserializer (SerDes) transceiver with controller and physical layer (PHY) is presented.The controller mainly contains protocol transmission, forward error correction and user layer build-in self-test (BIST).The physical coding sub-layer (PCS) provides the functions of 64/66 encoder/decoder, PHY BIST, and polarity control.In the physical medium attachment (PMA), both transmitter (TX) and receiver (RX) adopt quarter-rate architecture to relax the timing constraint and reduce power dissipation.The receiver utilizes the phase interpolator (PI) based clock and data recovery (CDR) with bang-bang phase detector (BBPD) to extract the synchronic clock for retiming and de-multiplexing.The multiple-MUX based 4-tap FFE and a two-stage cascade CTLE are employed to mitigate the inter-symbol interference (ISI).In addition, a proposed 4∶1 MUX is used to improve the output jitter performance and reduce the power consumption.Fabricated in a 65 nm CMOS technology, the full transceiver consumes 890 mW at 40 Gb/s and occupies 12 mm 2 .The measurement results show that this transceiver can achieve bit error rate (BER)< 10 -12 after a 15.3 dB loss channel at 20 GHz.

Multi-frequency point supported LLRF front-end for CiADS wide-bandwidth application

The China initiative Accelerator Driven System,CiADS,physics design adopts 162.5 MHz,325 MHz,and 650 MHz cavities,which are driven by the corresponding radio frequency(RF)power system,requiring frequency translation front-end for the RF station.For that application,a general-purpose design front-end prototype has been developed to evaluate the multi-frequency point supported design feasibility.The difficult parts to achieve the requirements of the general-purpose design are reasonable device selection and balanced design.With a carefully selected low-noise wide-band RF mixer and amplifier to balance the performance of multi-frequency supported down-conversion,specially designed LO distribution net to increase isolation between adjacent channels,and external band-pass filter to realize expected up-conversion frequencies,high maintenance and modular front-end generalpurpose design has been implemented.Results of standard parameters show an R2 value of at least 99.991%in the range of-60-10 dBm for linearity,up to 18 dBm for P1dB,and up to 89 dBc for cross talk between adjacent channels.The phase noise spectrum is lower than 80 dBc in the range of 0-1 MHz;cumulative phase noise is 0.006°;and amplitude and phase stability are 0.022%and 0.034°,respectively.

An analog front-end circuit for ISO/IEC 15693-compatible RFID transponder IC

The 13.56 MHz analog front-end circuit for ISO/IEC 15693-compatible radio frequency identification (RFID) trans- ponder IC presented in this paper converts RF power to DC and extracts clock and data from the interrogator by 10% or 100% ASK modulation. The transponder sends data back to the interrogator by load modulation technology. The electrostatic discharge (ESD) protection circuits function to limit RF voltage to a safe level. An inductive coupling simulation modelling for 13.56 MHz RFID system is presented, with simulation results showing that the transponder operates over a wide range of electromagnetic field strength from Hmin (150 mA/m) to Hmax (5 A/m). The transponder IC is implemented in SMIC 0.35-μm three-metal two-poly mixed signal CMOS technology with embedded EEPROM.

Design of 60GHz RF Transceiver in CMOS:Challenges and Recent Advances

With more scaling, the speed of than 40 years Moore CMOS transistors is around 100 GHz. Such fact makes it possible to realize mm-wave circuits in CMOS. However, with the target of achieving broadband and power-efficient operation, 60 GHz CMOS RF transceiver faces severe challenges. After reviewing the technology issues, regarding the 60 GHz applications, this paper discusses design challenges both from the system and the building block levels, and also presents some simulated or measured circuits results.

Silicon photonic transceivers for application in data centers

Global data traffic is growing rapidly,and the demand for optoelectronic transceivers applied in data centers(DCs)is also increasing correspondingly.In this review,we first briefly introduce the development of optoelectronics transceivers in DCs,as well as the advantages of silicon photonic chips fabricated by complementary metal oxide semiconductor process.We also summarize the research on the main components in silicon photonic transceivers.In particular,quantum dot lasers have shown great potential as light sources for silicon photonic integration—whether to adopt bonding method or monolithic integration—thanks to their unique advantages over the conventional quantum-well counterparts.Some of the solutions for highspeed optical interconnection in DCs are then discussed.Among them,wavelength division multiplexing and four-level pulseamplitude modulation have been widely studied and applied.At present,the application of coherent optical communication technology has moved from the backbone network,to the metro network,and then to DCs.