Rail-to-rail op-amp with constant transconductance,SR and gain

A novel general-purpose low-voltage rail-to-rail CMOS （ complementary metal-oxide-semiconductor transistor ） operational amplifier （op-amp）is introduced, which obtains constant transconductance, slew rate and constant high gain over the entire input common mode voltage range. The proposed scheme has the potential for applications in deep submicrometer technology, as the operation of the circuit does not exclusively rely on the square-law or the linear-law of transistors. The scheme is compact and suitable for applications as VLSI cell. The rail-to- rail op-amp has been implemented in DPDM 0. 6 μm mixedsignal process. The simulations show that in the entire range of input common mode voltage, the variations in transconductance, SR and gain are 1%, 2. 3%, 1.36 dB, respectively. Based on this, the layout and tape-out are carded out. The area of layout is 0. 072 mm^2. The test results are basically consistent with the circuit simulation.

High Transconductance AlGaN/GaN HEMT Growth on Sapphire Substrates

The fabrication and characterization of AlGaN/GaN high electron mobility transistors (HEMT) grown on sapphire substrates by MBE are described.These 1.0μm gate-length devices exhibit a maximum drain current density as high as 1000mA/mm and a maximum transconductance of 198mS/mm.In sharp c ontrast to high current density HEMT fabricated on sapphire substrates,the extrinsic transconductance versus gate-to-source voltage profiles exhibit the broad plateaus over a large voltage swing.A unity gain cutoff frequency (f T) of 18.7GHz and a maximum frequency of oscillation (f max) of 19.1GHz are also obtained.

Bias Current Compensation Method with 41.4% Standard Deviation Reduction to MOSFET Transconductance in CMOS Circuits

A simple and successful method for the stability enhancement of integrated circuits is presented. When the process parameters, temperature, and supply voltage are changed, according to the simulation results, this method yields a standard deviation of the transconductance of MOSFETs that is 41.4% less than in the uncompensated case. This method can be used in CMOS LC oscillator design.

Negative transconductance effect in p-GaN gate AlGaN/GaN HEMTs by traps in unintentionally doped GaN buffer layer

We investigate the negative transconductance effect in p-GaN gate AlGaN/GaN high-electron-mobility transistor(HEMT) associated with traps in the unintentionally doped GaN buffer layer. We find that a negative transconductance effect occurs with increasing the trap concentration and capture cross section when calculating transfer characteristics.The electron tunneling through AlGaN barrier and the reduced electric field discrepancy between drain side and gate side induced by traps are reasonably explained by analyzing the band diagrams, output characteristics, and the electric field strength of the channel of the devices under different trap concentrations and capture cross sections.

Degradation of the transconductance of a gate-modulated generation current in nMOSFET

The degradation of transconductance （G） of a gate-modulated generation current IGD in a LDD nMOSFET is investigated. The G curve shifts rightward under the single electron-injection-stress （EIS）. The trapped electrons located in the gate oxide over the LDD region （QL） makes the effective drain voltage diminish. Accordingly, the G peak in depletion （GMD） and that in weak inversion （GMw） decrease. It is found that △GMD and △GMw each have a linear relationship with the n-th power of stress time （tn） in a dual-log coordinate： △GMD octn, AGMD octn （n = 0.25）. During the alternate stress, the injected holes neutralize QL induced by the previous EIS. This neutralization makes the effective VD restore to the initial value and then the IGD peak recovers completely. Yet the threshold voltage recovery is incomplete due to the trapped electron located over the channel （Qc）. As a result, GMW only recovers to circa 50% of the initial value after the hole-injection-stress （HIS）. Instead, GMD almost recovers. The relevant mechanisms are given in detail.

Efficient Slew-Rate Enhanced Operational Transconductance Amplifier

Today, along with the prevalent use of portable equipment, wireless, and other battery powered systems, the demand for amplifiers with a high gain-bandwidth product（GBW）, slew rate（SR）, and at the same time very low static power dissipation is growing. In this work, an operational transconductance amplifier（OTA） with an enhanced SR is proposed. By inserting a sensing resistor in the input port of the current mirror in the OTA, the voltage drop across the resistor is converted into an output current containing a term in proportion to the square of the voltage, and then the SR of the proposed OTA is significantly enhanced and the current dissipation can be reduced. The proposed OTA is designed and simulated with a 0.5μm complementary metal oxide semiconductor（CMOS） process. The simulation results show that the SR is 4.54V/μs, increased by 8.25 times than that of the conventional design, while the current dissipation is only 87.3%.

PARASITIC TOLERANT DIFFERENTIAL SC TRANSCONDUCTANCE USING UNITY GAIN BUFFERS

The unity gain buffer will be good to design high frequency SCF if its resistiveeffects can be eliminated,and therefore the whole parasitic sensitivities will greatly be reduced.On the basis of this concept,a novel parasitic tolerant SC DTE(differential transconductanceelement)is proposed.SC floating inductor and integrator fit for high frequency applications areformed by the DTE.The computer simulation and experiment on a third order elliptic LP filterverify its validity.

Numerical simulation of transconductance of AlGaN/GaN heterojunction field effect transistors at high temperatures

Based on the investigation of the influence of temperatures on parameters, including polarization, electron mobility, thermal conductivity, and conduction band discontinuity at the interface between AlGaN and GaN, the temperature dependence of transconductance for AlGaN/GaN heterojunction field effect transistors （HFETs） has been obtained by using a quasi-two-dimensional approach, and the calculated results are in good agreement with the experimental data. The reduction in transconductance at high temperatures is primarily due to the decrease in electron mobility in the channel. Calculations also demonstrate that the self-heating effect becomes serious as environment temperature increases.

Realization of a New Current Mode Second-Order Biquad Using Two Current Follower Transconductance Amplifiers (CFTAs)

A new circuit for realization of universal current-mode filter using current Follower Transconductance Amplifiers (CFTAs) is presented. The proposed circuit realizes current-mode low pass, high pass and band pass filter functions simultaneously with a single current source at the input. The band reject and all pass filters can also be obtained from the proposed circuit without any extra hardware. The proposed circuit employs three passive grounded elements and two CFTAs. Linear electronic control of natural frequency ω0 is available in the proposed circuit. The quality factor can be independently adjusted through grounded resistor. The proposed circuit employs two grounded capacitors and a grounded resistor along with two CFTAs. The grounded resistor can be replaced by an OTA based circuit for linear electronic control of quality factor Q0. The circuit exhibits low active and passive sensitivities for ω0 and Q0. Simulation results are obtained using PSPICE software which is in conformity with the theoretical findings.

Current Mode Universal Filter Using Single Current Controlled Differential Difference Current Conveyor Transconductance Amplifier

This research paper contains a new electronically tunable current-mode biquadratic universal filter using a new active building block;current controlled differential difference current conveyor transconductance amplifier (CCDDCCTA). The proposed filter provides the following important and desirable features: (i) One can use only one CCDDCCTA and two capacitors;(ii) One can get low pass (LP), band pass (BP), high pass (HP), notch (NF) and all pass (AP) current responses from the same configuration without any alteration;(iii) Passive components are grounded, which ease the integrated circuit implementation;(iv) Responses are electronically tunable;and (v) Sensitivity is low. Moreover, the non-ideality analysis shows that the parasitic passive components can be compensated for the proposed circuit. The functionality of the design is verified through SPICE simulations using 0.25 μm CMOS TSMC technology process parameters. Simulation result agrees well with the theoretical analysis.

New Voltage Mode Sinusoidal Oscillator Using Voltage Differencing Transconductance Amplifiers (VDTAs)

The purpose of this paper is to introduce a new electronically controlled voltage mode sinusoidal oscillator (VMSO) using Voltage Differencing Transconductance Amplifiers (VDTA). The proposed circuit provides electronic control of ω0 and independent condition of oscillation (CO). It is found that the oscillator works very satisfactorily and pure sinusoidal waveforms are available at the outputs. The PSPICE simulation confirms the theoretical results. The proposed oscillator circuit employs only two VDTAs, along with two grounded capacitor and single grounded resistor. The circuit exhibits low active and passive sensitivities for ω0. Simulation results are obtained by using PSPICE software with TSMC CMOS 0.18 um process parameters.

Design of CMOS Mixer with Complementary Transconductance

A current bleeding CMOS mixer with complementary transconductance stage is presented in this paper.The conversion gain of the mixer is increased and the flick noise of the mixer is reduced by inserting the PMOS to form current bleeding circuit in Gilbert mixer.The circuit is designed through SMIC 0.18um CMOS process,the LO frequency is 1.571GHz,RF frequency is 1.575GHz,simulation results show the conversion gain of the mixer is 18.5 dB,SSB NF is about 9.59dB,and third-order input intercept point(IIP3) is-4.6dBm.The mixer consumes 7.8 mA at 1.8 V power supply and the size of the whole layout is 0.73mm×0.68 mm.

基于电流模结构的超宽带无源混频器设计

采用SMIC 55 nm CMOS工艺,提出基于电流模结构的2~8 GHz超宽带高线性度直接下变频无源混频器结构.本设计主要结构为低噪声跨导放大器(low noise transconductance amplifier,LNTA)驱动I/Q两路电流模无源混频器,负载为低输入阻抗的跨阻放大器(trans-impedance amplifier,TIA),即LNTA-Passive Mixer-TIA结构.LNTA采用电容交叉耦合以及双端正反馈结构,解决阻抗匹配以及噪声等关键参数的折中问题.整个接收机链路获得较好的线性度及噪声性能,对于电源电压以及衬底噪声的鲁棒性也有所提升.后仿结果表明,在电源电压1.2 V情况下,射频输入信号频率为2~8 GHz,1 dB压缩点为−5.5 dBm,带内输入三阶交调点为−1 dBm,整体噪声系数为4 dB,核心版图面积为0.12 mm^(2).

SiC MOSFET开关瞬态解析建模综述

在评估和优化半导体器件开关瞬态特性领域,解析模型因具有简单、直观、应用便捷等优点得到广泛研究。相较同等功率等级的硅基功率器件,碳化硅(silicon carbide,SiC)金属氧化物半导体场效应晶体管(metal-oxide-semiconductor field effect transistor,MOSFET)可以应用于更高开关速度,其开关瞬态特性更为复杂,开关瞬态解析建模也更加困难。该文总结现有的针对SiC MOSFET与二极管换流对的开关瞬态解析建模方法,在建模过程中依次引入各种简化假设,按照简化程度由低到高的顺序,梳理解析建模的逐步简化过程。通过对比,评估各模型的优缺点以及适用场合,对其中准确性、实用性都较强的分段线性模型进行详细介绍;之后,对开关瞬态建模中关键参数的建模方法进行总结与评价;最后,指出现有SiC MOSFET开关瞬态解析模型中存在的问题,并对其未来发展给出建议。

AlN/β-Ga_(2)O_(3)HEMT直流特性仿真

本文利用器件仿真软件对AlN/β-Ga_(2)O_(3)高电子迁移率晶体管(HEMT)器件的直流特性进行研究。由于AlN具有很强的极化效应,在AlN/β-Ga_(2)O_(3)异质结界面处产生高浓度二维电子气(2DEG),使AlN/β-Ga_(2)O_(3)异质结基HEMT具有更加优越的器件性能。理论计算得到AlN/β-Ga_(2)O_(3)异质结界面处产生的面电荷密度为2.75×10^(13) cm^(-2)。通过分析器件的能带结构、沟道电子浓度分布,研究AlN势垒层厚度、栅极长度、栅漏间距,以及金属功函数等参数对器件转移特性和输出特性的影响。结果表明:随着AlN势垒层厚度的增大,阈值电压减小,最大跨导减小,沟道电子浓度增大使饱和漏电流增大;随着栅极长度缩短,跨导增大,当栅极长度缩短至0.1μm时,器件出现了短沟道效应,并且随着栅极长度的缩短,栅下沟道区电子浓度增大,而电子速度基本不变,导致饱和漏电流增大,导通电阻减小,并且器件的饱和特性变差;随着栅漏间距的增大,跨导增大,沟道区电子浓度不变,而电子速度略有增加,导致饱和漏电流增大;肖特基栅金属功函数的增加会增大阈值电压,不会改变器件跨导,沟道电子浓度减小导致饱和漏电流减小。上述结论为后面的器件的优化改进提供了理论依据。

适用于WLAN接收机的高线性电流模式混频器设计

针对无线局域网接收机对低成本和线性度的定制化需求,设计了一款适用于IEEE 802.11 b/g/n/ax标准WLAN接收机的高线性度电流模式混频器;采用零中频接收机架构,电流模式混频器的电路结构主要包括跨导级放大器,混频开关级和跨阻放大器;通过跨导级两种工作状态的转换和跨阻放大器反馈电阻的两种取值变化实现了混频器的四档增益可调;混频开关级选用双平衡无源混频电路以提供良好的线性度;为了解决零中频接收机存在的直流失调问题,加入了一种电流注入式的直流失调校准电路,进一步提高了混频器的线性度;对跨阻放大器中的跨导运算放大器电路进行优化设计以提高其带宽,使跨阻放大器的输入阻抗足够小以保证混频器的线性度;基于180 nm RF CMOS工艺,对混频器进行仿真:当本振频率为2.4 GHz时,四档增益分别为38、32、27和21 dB,中频带宽可达20 MHz;噪声系数在高增益的情况下为8.46 dB,输入三阶交调点在低增益的情况下可达13.72 dBm;仿真结果表明,在较宽的中频带宽下,电流模式混频器取得了良好的线性度性能,满足WLAN接收机的定制化需求。

基于电阻补偿跨导放大器的忆阻电路

忆阻器具有独特的记忆特性和非线性特征,被广泛应用在非易失存储器、神经网络、非线性系统等领域。提出了一种集成忆阻电路,该电路采用运算跨导放大器和电容积分电路实现忆阻特性,其中运算跨导放大器采用补偿电阻提高带宽,实现扩展工作频率范围的目的。忆阻电路基于SMIC 180 nm CMOS工艺设计实现,采用0.9 V双供电电源,可完全集成于芯片中,最高工作频率可达到100 MHz,功耗仅为0.252 mW。

一种非匹配模式恒定跨导的轨到轨运算放大器

针对传统轨到轨运算放大器输入级跨导恒定受工艺影响,提出了一种非匹配模式低失调恒定跨导轨到轨运算放大器,输入级电路采用最大电流控制法。该运放通过对P输入对管电流的监测,来控制N输入对管的电流,从而实现与工艺无关的恒定跨导的要求。输出级采用折叠式共源共栅的有源负载与AB类控制的输出级结合,提高电压增益,增加电压输出动态范围。运放基于DB Hitek 0.18μm工艺完成电路设计。仿真结果表明:在电源电压为+2.5 V和−2.5 V时,该运放的共模输入范围为−2.5~2.5 V,动态输出范围为−2.5~2.5 V,平均输入失调电压为12.7μV,开环增益为98 dB,相位裕度为73.1°,带宽为73.1 MHz,电源抑制比为90 dB,共模抑制比为95 dB,压摆率为57.1 V/μs,跨导变化率仅为4.9%,满足了恒定跨导的要求。