High-Performance Organic Field-Effect Transistors Based on Two-Dimensional Vat Orange 3 Crystals

The exploration and research of low-cost,environmentally friendly,and sustainable organic semiconductor materials are of immense significance in various fields,including electronics,optoelectronics,and energy conversion.Unfortunately,these semiconductors have almost poor charge transport properties,which range from∼10^(−4) cm^(2)·V^(−1)·s^(−1) to∼10^(−2) cm^(2)·V^(−1)·s^(−1).Vat orange 3,as one of these organic semiconductors,has great potential due to its highly conjugated structure.We obtain high-quality multilayered Vat orange 3 crystals with two-dimensional(2D)growth on h-BN surfaces with thickness of 10–100 nm using physical vapor transport.Raman’s results confirm the stability of the chemical structure of Vat orange 3 during growth.Furthermore,by leveraging the structural advantages of 2D materials,an organic field-effect transistor with a 2D vdW vertical heterostructure is further realized with h-BN encapsulation and multilayered graphene contact electrodes,resulting in an excellent transistor performance with On/Off ratio of 104 and high field-effect mobility of 0.14 cm^(2)·V^(−1)·s^(−1).Our results show the great potential of Vat orange 3 with 2D structures in future nano-electronic applications.Furthermore,we showcase an approach that integrates organic semiconductors with 2D materials,aiming to offer new insights into the study of organic semiconductors.

Effect of external magnetic field on the instability of THz plasma waves in nanoscale graphene field-effect transistors

The instability of plasma waves in the channel of field-effect transistors will cause the electromagnetic waves with THz frequency.Based on a self-consistent quantum hydrodynamic model,the instability of THz plasmas waves in the channel of graphene field-effect transistors has been investigated with external magnetic field and quantum effects.We analyzed the influence of weak magnetic fields,quantum effects,device size,and temperature on the instability of plasma waves under asymmetric boundary conditions numerically.The results show that the magnetic fields,quantum effects,and the thickness of the dielectric layer between the gate and the channel can increase the radiation frequency.Additionally,we observed that increase in temperature leads to a decrease in both oscillation frequency and instability increment.The numerical results and accompanying images obtained from our simulations provide support for the above conclusions.

High performance carrier stored trench bipolar transistor with dual shielding structure

We propose a novel high performance carrier stored trench bipolar transistor(CSTBT)with dual shielding structure(DSS-CSTBT).The proposed DSS-CSTBT features a double trench structure with different trench profiles in the surface,in which a shallow gate trench is shielded by a deep emitter trench and a thick oxide layer under it.Compared with the conventional CSTBT(con-CSTBT),the proposed DSS-CSTBT not only alleviates the negative impact of the shallow gate trench and highly doped CS layer on the breakdown voltage(BV),but also well reduces the gate-collector capacitance CGC,gate charge Q_(G),and turn-off loss E_(OFF)of the device.Furthermore,lower turn-on loss E_(ON)and gate drive loss E_(DR)are also obtained.Simulation results show that with the same CS layer doping concentration N_(CS)=1.5×10^(16)cm^(-3),the BV increases from 1312 V of the con-CSTBT to 1423 V of the proposed DSS-CSTBT with oxide layer thickness under gate(T_(og2))of 1μm.Moreover,compared with the con-CSTBT,the C_(GC)at V_(CE)of 25 V and miller plateau charge(Q_(GC))for the proposed DSS-CSTBT with T_(og2)of 1μm are reduced by 79.4%and 74.3%,respectively.With the VGEincreases from 0 V to 15 V,the total QGfor the proposed DSS-CSTBT with T_(og2)of 1μm is reduced by 49.5%.As a result,at the same on-state voltage drop(V_(CEON))of 1.55 V,the E_(ON)and E_(OFF)are reduced from 20.3 mJ/cm^(2)and 19.3 mJ/cm^(2)for the con-CSTBT to8.2 mJ/cm^(2)and 9.7 mJ/cm^(2)for the proposed DSS-CSTBT with T_(og2)of 1μm,respectively.The proposed DSS-CSTBT not only significantly improves the trade-off relationship between the V_(CEON)and E_(OFF)but also greatly reduces the E_(ON).

Atomic layer deposition for nanoscale oxide semiconductor thin film transistors:review and outlook

Since the first report of amorphous In–Ga–Zn–O based thin film transistors,interest in oxide semiconductors has grown.They offer high mobility,low off-current,low process temperature,and wide flexibility for compositions and processes.Unfortunately,depositing oxide semiconductors using conventional processes like physical vapor deposition leads to problematic issues,especially for high-resolution displays and highly integrated memory devices.Conventional approaches have limited process flexibility and poor conformality on structured surfaces.Atomic layer deposition(ALD)is an advanced technique which can provide conformal,thickness-controlled,and high-quality thin film deposition.Accordingly,studies on ALD based oxide semiconductors have dramatically increased recently.Even so,the relationships between the film properties of ALD-oxide semiconductors and the main variables associated with deposition are still poorly understood,as are many issues related to applications.In this review,to introduce ALD-oxide semiconductors,we provide:(a)a brief summary of the history and importance of ALD-based oxide semiconductors in industry,(b)a discussion of the benefits of ALD for oxide semiconductor deposition(in-situ composition control in vertical distribution/vertical structure engineering/chemical reaction and film properties/insulator and interface engineering),and(c)an explanation of the challenging issues of scaling oxide semiconductors and ALD for industrial applications.This review provides valuable perspectives for researchers who have interest in semiconductor materials and electronic device applications,and the reasons ALD is important to applications of oxide semiconductors.

Moiré Synaptic Transistor for Homogeneous-Architecture Reservoir Computing

Reservoir computing has been considered as a promising intelligent computing paradigm for effectively processing complex temporal information.Exploiting tunable and reproducible dynamics in the single electronic device have been desired to implement the “reservoir” and the “readout” layer of reservoir computing system.Two-dimensional moiré materials,with an artificial lattice constant many times larger than the atomic length scale,are one type of most studied artificial quantum materials in community of material science and condensed-matter physics over the past years.These materials are featured with gate-tunable periodic potential and electronic correlation,thus varying the electric field allows the electrons in the moiré potential per unit cell to exhibit distinct and reproducible dynamics,showing great promise in robust reservoir computing.Here,we report that a moiré synaptic transistor can be used to implement the reservoir computing system with a homogeneous reservoir-readout architecture.The synaptic transistor is fabricated based on an h-BN/bilayer graphene/h-BN moiré heterostructure,exhibiting ferroelectricity-like hysteretic gate voltage dependence of resistance.Varying the magnitude of the gate voltage enables the moiré transistor to switch between long-term memory and shortterm memory with nonlinear dynamics.By employing the short-and long-term memories as the reservoir nodes and weights of the readout layer,respectively,we construct a full-moiré physical neural network and demonstrate that the classification accuracy of 90.8% can be achieved for the MNIST(Modified National Institute of Standards and Technology) handwritten digits database.Our work would pave the way towards the development of neuromorphic computing based on moiré materials.

Stretchable organic electrochemical transistors with micro-/nano-structures

Organic electrochemical transistors(OECTs)have attracted attention due to their unique function of converting ionic and biological signals into electronic signals,high transconductance,low energy consumption(below 1 V),stable operation in aqueous media,good biocompatibility[1,2].However,most OECTs are usually built on brittle and stiff substrates,and inappropriate to be adhered to or contacted with delicate human skin,thus impeding their use in wearable electronics.It is desirable to exploit stretchable OECTs to reduce the mechanical mismatch with soft tissues.

P-type cold-source field-effect transistors with TcX_(2) and ReX_(2)(X=S,Se)cold source electrodes:A computational study

Cold-source field-effect transistors(CS-FETs)have been developed to overcome the major challenge of power dissipation in modern integrated circuits.Cold metals suitable for n-type CS-FETs have been proposed as the ideal electrode to filter the high-energy electrons and break the thermal limit on subthreshold swing(SS).In this work,regarding the p-type CS-FETs,we propose TcX_(2) and ReX_(2)(X=S,Se)as the injection source to realize the sub-thermal switching for holes.First-principles calculations unveils the cold-metal characteristics of monolayer TcX_(2) and ReX_(2),possessing a sub-gap below the Fermi level and a decreasing DOS with energy.Quantum device simulations demonstrate that TcX_(2) and ReX_(2) can enable the cold source effects in WSe_(2) p-type FETs,achieving steep SS of 29-38 mV/dec and high on/off ratios of(2.3-5.6)×10^(7).Moreover,multilayer Re S2retains the cold metal characteristic,thus ensuring similar CS-FET performances to that of the monolayer source.This work underlines the significance of cold metals for the design of p-type CS-FETs.

Homojunction structure amorphous oxide thin film transistors with ultra-high mobility

Amorphous oxide semiconductors(AOS)have unique advantages in transparent and flexible thin film transistors(TFTs)applications,compared to low-temperature polycrystalline-Si(LTPS).However,intrinsic AOS TFTs are difficult to obtain field-effect mobility(μFE)higher than LTPS(100 cm^(2)/(V·s)).Here,we design ZnAlSnO(ZATO)homojunction structure TFTs to obtainμFE=113.8 cm^(2)/(V·s).The device demonstrates optimized comprehensive electrical properties with an off-current of about1.5×10^(-11)A,a threshold voltage of–1.71 V,and a subthreshold swing of 0.372 V/dec.There are two kinds of gradient coupled in the homojunction active layer,which are micro-crystallization and carrier suppressor concentration gradient distribution so that the device can reduce off-current and shift the threshold voltage positively while maintaining high field-effect mobility.Our research in the homojunction active layer points to a promising direction for obtaining excellent-performance AOS TFTs.

Charge trapping effect at the interface of ferroelectric/interlayer in the ferroelectric field effect transistor gate stack

We study the charge trapping phenomenon that restricts the endurance of n-type ferroelectric field-effect transistors(FeFETs)with metal/ferroelectric/interlayer/Si(MFIS)gate stack structure.In order to explore the physical mechanism of the endurance failure caused by the charge trapping effect,we first establish a model to simulate the electron trapping behavior in n-type Si FeFET.The model is based on the quantum mechanical electron tunneling theory.And then,we use the pulsed I_d-V_g method to measure the threshold voltage shift between the rising edges and falling edges of the FeFET.Our model fits the experimental data well.By fitting the model with the experimental data,we get the following conclusions.(i)During the positive operation pulse,electrons in the Si substrate are mainly trapped at the interface between the ferroelectric(FE)layer and interlayer(IL)of the FeFET gate stack by inelastic trap-assisted tunneling.(ii)Based on our model,we can get the number of electrons trapped into the gate stack during the positive operation pulse.(iii)The model can be used to evaluate trap parameters,which will help us to further understand the fatigue mechanism of FeFET.

Ultrasensitive detection of methamphetamine by antibody-modified transistor assay

Effective detection of methamphetamine(Met)requires a fast,sensitive,and cheap testing assay.However,commercially available methods require expensive instruments and highly trained operators,which are time-consuming and labor-intensive.Herein,an antibody-modified graphene transistor assay is developed for sensitive and minute-level detection of Met in complex environments.The anti-Met probe captured charged targets within 120 s,leading to a p-doping effect near the graphene channel.The limit of detection reaches 50 aM(5.0×10^(-17)M)Met in solution.The graphene transistor would be a valuable tool for Met detection effective prevention of drug abuse.

Si–Ge based vertical tunnel field-effect transistor of junction-less structure with improved sensitivity using dielectric modulation for biosensing applications

A dielectric modulation strategy for gate oxide material that enhances the sensing performance of biosensors in junction-less vertical tunnel field effect transistors(TFETs)is reported.The junction-less technique,in which metals with specific work functions are deposited on the source region to modulate the channel conductivity,is used to provide the necessary doping for the proper functioning of the device.TCAD simulation studies of the proposed structure and junction structure have been compared,and showed an enhanced rectification of 10^(4) times.The proposed structure is designed to have a nanocavity of length 10 nm on the left-and right-hand sides of the fixed gate dielectric,which improves the biosensor capture area,and hence the sensitivity.By considering neutral and charged biomolecules with different dielectric constants,TCAD simulation studies were compared for their sensitivities.The off-state current IOFFcan be used as a suitable sensing parameter because it has been observed that the proposed sensor exhibits a significant variation in drain current.Additionally,it has been investigated how positively and negatively charged biomolecules affect the drain current and threshold voltage.To explore the device performance when the nanogaps are fully filled,half filled and unevenly filled,extensive TCAD simulations have been run.The proposed TFET structure is further benchmarked to other structures to show its better sensing capabilities.

High-performance vertical GaN field-effect transistor with an integrated self-adapted channel diode for reverse conduction

A vertical GaN field-effect transistor with an integrated self-adapted channel diode(CD-FET)is proposed to improve the reverse conduction performance.It features a channel diode(CD)formed between a trench source on the insulator and a P-type barrier layer(PBL),together with a P-shield layer under the trench gate.At forward conduction,the CD is pinched off due to depletion effects caused by both the PBL and the metal-insulator-semiconductor structure from the trench source,without influencing the on-state characteristic of the CD-FET.At reverse conduction,the depletion region narrows and thus the CD turns on to achieve a very low turn-on voltage(V_(F)),preventing the inherent body diode from turning on.Meanwhile,the PBL and P-shield layer can modulate the electric field distribution to improve the off-state breakdown voltage(BV).Moreover,the P-shield not only shields the gate from a high electric field but also transforms part of C_(GD)to CGS so as to significantly reduce the gate charge(Q_(GD)),leading to a low switching loss(E_(switch)).Consequently,the proposed CD-FET achieves a low V_(F)of 1.65 V and a high BV of 1446 V,and V_(F),Q_(GD)and E_(switch)of the CD-FET are decreased by 49%,55%and 80%,respectively,compared with those of a conventional metal-oxide-semiconductor field-effect transistor(MOSFET).

A non-quasi-static model for nanowire gate-all-around tunneling field-effect transistors

Nanowires with gate-all-around(GAA) structures are widely considered as the most promising candidate for 3-nm technology with the best ability of suppressing the short channel effects,and tunneling field effect transistors(TFETs)based on GAA structures also present improved performance.In this paper,a non-quasi-static(NQS) device model is developed for nanowire GAA TFETs.The model can predict the transient current and capacitance varying with operation frequency,which is beyond the ability of the quasi-static(QS) model published before.Excellent agreements between the model results and numerical simulations are obtained.Moreover,the NQS model is derived from the published QS model including the current-voltage(I-V) and capacitance-voltage(C-V) characteristics.Therefore,the NQS model is compatible with the QS model for giving comprehensive understanding of GAA TFETs and would be helpful for further study of TFET circuits based on nanowire GAA structure.

Temperature dependence of single-event transients in SiGe heterojunction bipolar transistors for cryogenic applications

We experimentally demonstrate that the dominant mechanism of single-event transients in silicon-germanium heterojunction bipolar transistors(SiGe HBTs)can change with decreasing temperature from+20℃to-180℃.This is accomplished by using a new well-designed cryogenic experimental system suitable for a pulsed-laser platform.Firstly,when the temperature drops from+20℃to-140℃,the increased carrier mobility drives a slight increase in transient amplitude.However,as the temperature decreases further below-140℃,the carrier freeze-out brings about an inflection point,which means the transient amplitude will decrease at cryogenic temperatures.To better understand this result,we analytically calculate the ionization rates of various dopants at different temperatures based on Altermatt's new incomplete ionization model.The parasitic resistivities with temperature on the charge-collection pathway are extracted by a two-dimensional(2D)TCAD process simulation.In addition,we investigate the impact of temperature on the novel electron-injection process from emitter to base under different bias conditions.The increase of the emitter-base junction's barrier height at low temperatures could suppress this electron-injection phenomenon.We have also optimized the built-in voltage equations of a high current compact model(HICUM)by introducing the impact of incomplete ionization.The present results and methods could provide a new reference for effective evaluation of single-event effects in bipolar transistors and circuits at cryogenic temperatures,and could provide a new evidence of the potential of SiGe technology in applications in extreme cryogenic environments.

Low-temperature metal–oxide thin-film transistor technologies for implementing flexible electronic circuits and systems

Here we review two 300℃metal–oxide(MO)thin-film transistor(TFT)technologies for the implementation of flexible electronic circuits and systems.Fluorination-enhanced TFTs for suppressing the variation and shift of turn-on voltage(VON),and dual-gate TFTs for acquiring sensor signals and modulating VON have been deployed to improve the robustness and performance of the systems in which they are deployed.Digital circuit building blocks based on fluorinated TFTs have been designed,fabricated,and characterized,which demonstrate the utility of the proposed low-temperature TFT technologies for implementing flexible electronic systems.The construction and characterization of an analog front-end system for the acquisition of bio-potential signals and an active-matrix sensor array for the acquisition of tactile images have been reported recently.

Novel GaN-based double-channel p-heterostructure field-effect transistors with a p-GaN insertion layer

GaN-based p-channel heterostructure field-effect transistors(p-HFETs)face significant constraints on on-state currents compared with n-channel high electron mobility transistors.In this work,we propose a novel double heterostructure which introduces an additional p-GaN insertion layer into traditional p-HFETs.The impact of the device structure on the hole densities and valence band energies of both the upper and lower channels is analyzed by using Silvaco TACD simulations,including the thickness of the upper AlGaN layer and the doping impurities and concentration in the GaN buffer layer,as well as the thickness and Mg-doping concentration in the p-GaN insertion layer.With the help of the p-GaN insertion layer,the C-doping concentration in the GaN buffer layer can be reduced,while the density of the two-dimensional hole gas in the lower channel is enhanced at the same time.This work suggests that a double heterostructure with a p-GaN insertion layer is a better approach to improve p-HFETs compared with those devices with C-doped buffer layer alone.

Single-electron transport in H_(2)O@C_(60) single-molecule transistors

Single-molecule transistors(SMTs) based on fullerenes and their derivatives have been recognized as a long-sought platform for studying the single-electron transport properties.H_(2)O@C_(60) is a combination of fullerene and H_(2)O,a typical light molecule.Here we use the 'molecular surgery' technique to synthesize the H_(2)O@C_(60) molecule and then construct the H_(2)O@C_(60) SMTs,together with the C_(60) SMTs.Evidences for single-electron transport have been obtained in our measurements,including explicit Coulomb blockade and Coulomb oscillations.We then calculate the detailed parameters of the H_(2)O@C_(60) and C_(60) SMTs using a capacitance model derived from the Coulomb diamond feature,which gives a capacitance ratio of 1:5.05:8.52 for the H_(2)O@C_(60) SMT and 1:29.5:74.8 for the C_(60) SMT.Moreover,the gate efficiency factor a turns out to be 0.0686 in the H_(2)O@C_(60) SMT,about ten times larger than that in the C_(60) SMT.We propose that the enhanced gate efficiency in H_(2)O@C_(60) SMT may be induced by the closer attachment of molecular orbital electron clouds to the gate substrate due to polarization effects of H_(2)O.

Fluorination-mitigated high-current degradation of amorphous InGaZnO thin-film transistors

As growing applications demand higher driving currents of oxide semiconductor thin-film transistors(TFTs),severe instabilities and even hard breakdown under high-current stress(HCS)become critical challenges.In this work,the triggering voltage of HCS-induced self-heating(SH)degradation is defined in the output characteristics of amorphous indium-galliumzinc oxide(a-IGZO)TFTs,and used to quantitatively evaluate the thermal generation process of channel donor defects.The fluorinated a-IGZO(a-IGZO:F)was adopted to effectively retard the triggering of the self-heating(SH)effect,and was supposed to originate from the less population of initial deep-state defects and a slower rate of thermal defect transition in a-IGZO:F.The proposed scheme noticeably enhances the high-current applications of oxide TFTs.

High on-state current p-type tunnel effect transistor based on doping modulation

To solve the problem of the low on-state current in p-type tunnel field-effect transistors(p-TFETs),this paper analyzes the mechanism of adjusting the tunneling current of a TFET device determined by studying the influence of the peak position of ion implantation on the potential of the p-TFET device surface and the width of the tunneling barrier.Doping-regulated silicon-based high on-state p-TFET devices are designed and fabricated,and the test results show that the on-state current of the fabricated devices can be increased by about two orders of magnitude compared with the current of other devices with the same structure.This method provides a new idea for the realization of high on-state current TFET devices.

Design and Analysis of Graphene Based Tunnel Field Effect Transistor with Various Ambipolar Reducing Techniques

The fundamental advantages of carbon-based graphene material,such as its high tunnelling probability,symmetric band structure(linear dependence of the energy band on the wave direction),low effective mass,and characteristics of its 2D atomic layers,are the main focus of this research work.The impact of channel thickness,gate under-lap,asymmetric source/drain doping method,workfunction of gate contact,and High-K material on Graphene-based Tunnel Field Effect Transistor(TFET)is analyzed with 20 nm technology.Physical modelling and electrical characteristic performance have been simulated using the Atlas device simulator of SILVACO TCAD with user-defined material syntax for the newly included graphene material in comparison to silicon carbide(SiC).The simulation results in significant suppression of ambipolar current to voltage characteristics of TFET and modelled device exhibits a significant improvement in subthreshold swing(0.0159 V/decade),the ratio of Ion/Ioff(1000),and threshold voltage(-0.2 V with highly doped p-type source and 0.2 V with highly doped n-type drain)with power supply of 0.5 V,which make it useful for low power digital applications.