Shape Memory Polymer Composite Booms with Applications in Reel-Type Solar Arrays

Solar arrays are the primary energy source for spacecraft.Although traditional rigid solar arrays improve power supply,the quality increases proportionally.Hence,it is difficult to satisfy the requirements of high-power and low-cost space applications.In this study,a shape-memory polymer composite(SMPC)boom was designed,fabricated,and characterized for flexible reel-type solar arrays.The SMPC boom was fabricated from a smart material,a shape-memory polymer composite,whose mechanical properties were tested.Additionally,a mathematical model of the bending stiffness of the SMPC boom was developed,and the bending and buckling behaviors of the boom were further analyzed using the ABAQUS software.An SMPC boom was fabricated to demonstrate its shape memory characteristics,and the driving force of the booms with varying geometric parameters was investigated.We also designed and manufactured a reel-type solar array based on an SMPC boom and verified its self-deployment capability.The results indicated that the SMPC boom can be used as a deployable unit to roll out flexible solar arrays.

CNN Accelerator Using Proposed Diagonal Cyclic Array for Minimizing Memory Accesses

This paper presents the architecture of a Convolution Neural Network(CNN)accelerator based on a newprocessing element(PE)array called a diagonal cyclic array(DCA).As demonstrated,it can significantly reduce the burden of repeated memory accesses for feature data and weight parameters of the CNN models,which maximizes the data reuse rate and improve the computation speed.Furthermore,an integrated computation architecture has been implemented for the activation function,max-pooling,and activation function after convolution calculation,reducing the hardware resource.To evaluate the effectiveness of the proposed architecture,a CNN accelerator has been implemented for You Only Look Once version 2(YOLOv2)-Tiny consisting of 9 layers.Furthermore,the methodology to optimize the local buffer size with little sacrifice of inference speed is presented in this work.We implemented the proposed CNN accelerator using a Xilinx Zynq ZCU102 Ultrascale+Field Programmable Gate Array(FPGA)and ISE Design Suite.The FPGA implementation uses 34,336 Look Up Tables(LUTs),576 Digital Signal Processing(DSP)blocks,and an on-chip memory of only 58 KB,and it could achieve accuracies of 57.92% and 56.42% mean Average Precession@0.5 thresholds for intersection over union(mAP@0.5)using quantized 16-bit and 8-bit full integer data manipulation with only 0.68% as a loss for 8-bit version and computation time of 137.9 and 69 ms for each input image respectively using a clock speed of 200 MHz.These speeds are expected to be doubled five times using a clock speed of 1GHz if implemented in a silicon System on Chip(SoC)using a sub-micron process.

Design and Implementation of Memory Access Fast Switching Structure in Cluster-Based Reconfigurable Array Processor

Memory access fast switching structures in cluster are studied,and three kinds of fast switching structures( FS,LR2 SS,and LAPS) are proposed. A mixed simulation test bench is constructed and used for statistic of data access delay among these three structures in various cases. Finally these structures are realized on Xilinx FPGA development board and DCT,FFT,SAD,IME,FME,and de-blocking filtering algorithms are mapped onto the structures. Compared with available architectures,our proposed structures have lower data access delay and lower area.

TiOx-based self-rectifying memory device for crossbar WORM memory array applications

Resistive switching with a self-rectifying feature is one of the most effective solutions to overcome the crosstalk issue in a crossbar array. In this paper, a memory device based on Pt/TiO_(x)/W structure with self-rectifying property is demonstrated for write-once-read-many-times(WORM) memory application. After programming, the devices exhibit excellent uniformity and keep in the low resistance state(LRS) permanently with a rectification ratio as high as 10^(4) at ±1 V. The self-rectifying resistive switching behavior can be attributed to the Ohmic contact at TiO_(x)/W interface and the Schottky contact at Pt/TiO_(x) interface. The results in this paper demonstrate the potential application of TiO_(x)-based WORM memory device in crossbar arrays.

Temperature-insensitive reading of a flash memory cell

The temperature characteristics of the read current of the NOR embedded flash memory with a 1.5T-per-cell structure are theoretically analyzed and experimentally verified.We verify that for a cell programmed with a“10”state,the read current is either increasing,decreasing,or invariable with the temperature,essentially depending on the reading overdrive voltage of the selected bitcell,or its programming strength.By precisely controlling the programming strength and thus manipulating its temperature coefficient,we propose a new setting method for the reference cells that programs each of reference cells to a charge state with a temperature coefficient closely tracking tail data cells,thereby solving the current coefficient mismatch and improving the read window.

A shape-reconfigurable,light and magnetic dual-responsive shape-memory micropillar array chip for droplet manipulation

Droplet manipulation on an open surface has great potential in chemical analysis and biomedicine engineering.However,most of the reported platforms designed for the manipulation of water droplets cannot thoroughly solve the problem of droplet evaporation.Herein,we report a shape-reconfigurable micropillar array chip for the manipulation of water droplets,oil droplets and water-in-oil droplets.Water-in-oil droplets provide an enclosed space for water droplets,preventing the evaporation in an open environment.Perfluoropolyether coated on the surface of the chip effectively reduces the droplet movement resistance.The micropillar array chip has light and magnetic dual-response due to the Fe3O4 nanoparticles and the reduced iron powder mixed in the shape-memory polymer.The micropillars irradiated by a near-infrared laser bend under the magnetic force,while the unirradiated micropillars still keep their original shape.In the absence of a magnetic field,when the micropillars in a temporary shape are irradiated by the near-infrared laser to the transition temperature,the micropillars return to their initial shape.In this process,the surface morphology gradient caused by the deformation of the micropillars and the surface tension gradient caused by the temperature change jointly produce the driving force of droplet movement.

Design of a clustered data-driven array processor for computer vision

Computer vision(CV)is widely expected to be the next big thing in emerging applications.So many heterogeneous architectures for computer vision emerge.However,plenty of data need to be transferred between different structures for heterogeneous architecture.The long data transfer delay becomes the mainly problem to limit the processing speed for computer vision applications.For reducing data transfer delay and fasting computer vision applications,a clustered data-driven array processor is proposed.A three-level pipelining processing element is designed which supports two-buffer data flow interface and 8 bits,16 bits,32 bits subtext parallel computation.At the same time,for accelerating transcendental function computation,a four-way shared pipelining transcendental function accelerator is designed,which is based on Y-intercept adjusted piecewise linear segment algorithm.A distributed shared memory structure based on unified addressing is also employed.To verify efficiency of architecture,some image processing algorithms are implemented on proposed architecture.Simultaneously the proposed architecture has been implemented on Xilinx ZC 706 development board.The same circuitry has been synthesized using SMIC 130 nm CMOS technology.The circuitry is able to run at 100 MHz.Area is 26.58 mm2.

Calculation Method for Forced-Air Convection Cooling Heat Transfer Coefficient of Multiple Rows of Memory Cards

Forced-air convection cooling of high-power electronic devices is widely used, but it has a problem that a rise in temperature of the air used to cool the upstream devices decreases the cooling capa-bility for the downstream devices. In this study we made an experimental apparatus including a memory card array and measured the effect of the rise in temperature of the air on the heat transfer coefficient of the memory cards that were downstream in the air flow. Using these mea-surements, we devised a simple calculation model, called the thermal diffusion layer model, to calculate the heat transfer coefficient of multiple rows of memory cards. The rise in temperature of downstream memory cards due to higher temperature air can be evaluated with a parameter representing the delay of thermal mixing for air. The heat transfer coefficient calculated with the thermal diffusion layer model agreed with our experimental results.

In-memory computing to break the memory wall

Facing the computing demands of Internet of things(IoT)and artificial intelligence(AI),the cost induced by moving the data between the central processing unit(CPU)and memory is the key problem and a chip featured with flexible structural unit,ultra-low power consumption,and huge parallelism will be needed.In-memory computing,a non-von Neumann architecture fusing memory units and computing units,can eliminate the data transfer time and energy consumption while performing massive parallel computations.Prototype in-memory computing schemes modified from different memory technologies have shown orders of magnitude improvement in computing efficiency,making it be regarded as the ultimate computing paradigm.Here we review the state-of-the-art memory device technologies potential for in-memory computing,summarize their versatile applications in neural network,stochastic generation,and hybrid precision digital computing,with promising solutions for unprecedented computing tasks,and also discuss the challenges of stability and integration for general in-memory computing.

Structural Design of an Electrically Erasable EEPROM Memory Cell

EEPROM is an electrically erasable and programmable memory. The technology is mature and stable with low cost, so it is the mainstream in the application of electronic products in daily life. People use it in every way. In the fields of personal identity card, bank card, medical insurance card, traffic card and other smart cards, which are closely related to personal property, and in the field of communication system and other consumer electronic products such as PDA and digital camera, EEPROM is used. In instruments and other embedded systems, such as smart flowmeters, it is usually necessary to store information such as setting parameters, field data, etc., which requires that the system is not lost when it is powered down so that the data you originally set could be restored next time. Therefore, a certain capacity of?EEPROM.?Through the storage or release of electrons on the floating gate tube of the memory cell, the memory appears to be on or off when the floating gate tube is read, so its logic value will be judged as “0”?Or?“1”. The definition of logic “0” or “1” varies depending on the logical design of the product. This work designs a memory cell consisting of two transistors. The NMOS tube is used as a selection tube and controlled by the word line. It can withstand a part of the high voltage and reduce the probability of breakdown of the ultra-thin oxide layer of the floating gate transistor. As a storage tube, the EEPROM device model designed in this paper can work well through the tunnel oxide layer to store data, achieving better storage functions, higher work efficiency, and lower power consumption.

SRAM型FPGA单粒子辐照试验系统技术研究

单粒子辐射效应严重制约FPGA的空间应用,为提高FPGA在辐射环境中的可靠性,深入研究抗辐射加固FPGA单粒子效应评估方法,设计优化单粒子效应评估方案,开发相应的评估系统,提出基于SRAM时序修正的码流存储比较技术和基于SelectMAP端口配置回读技术。借助国内高能量大注量率的辐照试验环境,完成FPGA单粒子翻转(SEU)、单粒子闩锁(SEL)和单粒子功能中断(SEFI)等单粒子效应的检测,试验结果表明,该方法可以科学有效地对SRAM型FPGA抗单粒子辐射性能进行评估。

用FPGA实现嵌入式视频图像信号实时采集

提出了一种基于FPGA的嵌入式视频图像信号实时采集系统,采用SAA7111A对信号进行A/D变换,并用FPGA与SDRAM实现大容量的双帧缓存。详细说明双口存储器、有限状态机的实现及隔行扫描到逐行扫描的转换、乒乓互锁工作机制等。本系统可用在安全监控、工业图像检测、机器视觉等领域。

World’s first spaceflight on-orbit demonstration of a flexible solar array system based on shape memory polymer composites

With a 10%reversible compressive strain in more than 10 deformation cycles,the shape memory polymer composites(SMPCs)could be used for deployable structure and releasing mechanism.In this paper,without traditional electro-explosive devices or motors/controllers,the deployable SMPC flexible solar array system(SMPC-FSAS)is studied,developed,ground-based tested,and finally on-orbit validated.The epoxy-based SMPC is used for the rolling-out variable-stiffness beams as a structural frame as well as an actuator for the flexible blanket solar array.The releasing mechanism is primarily made of the cyanate-based SMPC,which has a high locking stiffness to withstand 50 g gravitational acceleration and a large unlocking displacement of 10 mm.The systematical mechanical and thermal qualification tests of the SMPC-FSAS flight hardware were performed,including sinusoidal sweeping vibration,shocking,acceleration,thermal equilibrium,thermal vacuum cycling,and thermal cycling test.The locking function of the SMPC releasing mechanisms was in normal when launching aboard the SJ20 Geostationary Satellite on 27 Dec.,2019.The SMPC-FSAS flight hardware successfully unlocked and deployed on 5 Jan.,2020 on geostationary orbit.The triggering signal of limit switches returned to ground at the 139 s upon heating,which indicated the successful unlocking function of SMPC releasing mechanisms.A pair of epoxy-based SMPC rolled variable-stiffness tubes,which clapped the flexible blanket solar array,slowly deployed and finally approached an approximate 100%shape recovery ratio within 60 s upon heating.The study and on-orbit successful validation of the SMPC-FSAS flight hardware could accelerate the related study and associated productions to be used for the next-generation releasing mechanisms as well as space deployable structures,such as new releasing mechanisms with low-shocking,testability and reusability,and ultra-large space deployable solar arrays.

GERO: a general SCA-based readout ASIC for micro-pattern gas detectors with configurable storage depth and on-chip digitizer

The paper presents GEneral ReadOut (GERO), a general readout ASIC based on a switched capacitor array for micro-pattern gas detectors. It aims at providing general readout electronics for low-to-medium event-rate gas detectors with high sampling frequency, configurable storage depth, and data digitalization. The first prototype GERO chip integrates 16 channels and was fabricated using a 0.18-lm CMOS process. Each channel consists of a sampling array working in a ping-pong mode, a storage array with a 1024-cell depth, and 32 Wilkinson analog-todigital converters. The detailed design and test results are presented in the paper.

A novel SRAM test method based on embeddedimplementation on FPGA

With the development of satellite based remote sensors, embedded systems become moreand more popular in space camera electronics. Static Random Access Memory（SRAM） is one kind of themost widely used memories due to its merits of high efficiency and low power dissipation, but testing itsfunction still depends on writing testing modules with hardware description language, which results in lowdeveloping efficiency and low reliability. In this paper, an embedded testing method is proposed, which isbased on MicroBlaze and its speed increasing function design. Implementation of the test method is basedon reusable Intellectual Property（IP） technique and greatly improves data transfer speed. With this method,secondary development of SRAM test system can be made in application layer instead of fundamentallogical layer, which simplifies the system design. It is not only more efficient and more reliable, but alsoeasier to transplant, which greatly reduces test design cost. The validity and feasibility of the method havebeen proved by test results.

Erosion thermocouple temperature acquisition system

Aiming at high requirements of temperature measurement system in high temperature,high pressure,highly corrosive and other special environments,a temperature acquisition system based on field-programmable gate array(FPGA) which is the controller of the system is designed.Also a Flash memory is used as the memory and an erosion thermocouple is used as sensor of the system.Compared with the traditional system using complex programmable logic device(CPLD)and microcontroller unit(MCU)as the main body,this system has some advantages,such as short response time,small volume,no loss of data once power is off,high precision,stability and reliability.And the sensor of the system can be reused.In this paper,boiling water experiment is used to verify accuracy of the system.The millisecond level signal from firecrackers is for verifying the stability and fast response characteristics of the system.The results of experiment indicate that the temperature measurement system is more suitable for the field of explosion and other environments which have high requirements for the system.

Low complexity SEU mitigation technique for SRAM-based FPGAs

An internal single event upset(SEU)mitigation technique is proposed,which reads back the configuration frames from the static random access memory(SRAM)-based field programmable gate array(FPGA)through an internal port and compares them with those stored in the radiationhardened memory to detect and correct SEUs.Triple modular redundancy(TMR),which triplicates the circuit of the technique and uses majority voters to isolate any single upset within it,is used to enhance the reliability.Performance analysis shows that the proposed technique can satisfy the requirement of ordinary aerospace missions with less power dissipation,size and weight.The fault injection experiment validates that the proposed technique is capable of correcting most errors to protect spaceborne facilities from SEUs.

Design of shared bus DSP board in vector network analyzer

Currently,the mainstream vector network analyzer employs embedded computer module with a digital intermediate frequency(IF)board to form a high performance windows platform.Under this structure,the vector network analyzer needs a powerful encoding system to arbitrate the bus acquirement,which is usually realized by field-programmable gate array(FPGA)chip.The paper explores the shared bus design method of the digital signal processing(DSP)board in network analyzer.Firsty,it puts an emphasis on the system structure,and then the shared bus communication method is described in detail;Finally,the advantages of the shared bus communication mechanism are summanzed.

LiNbO_3/p^+n diode surface acoustic wave memory correlator

A detailed theoretical analysis of strip-coupled LiNbO3/p+ n diode surface acoustic wave (SAW) memory correlator in the parametric mode is presented. The influence of some important factors on correlation output is analyzed and calculated, including the amplitudes of reference, read and write signal, duration of write signal and doping density of the diode array. The conclusions can be employed for the design of improved strip-coupled SAW memorycorrelators.

On the Current Error Based Sampled-data Iterative Learning Control with Reduced Memory Capacity

The design of iterative learning controller(ILC) requires to store the system input, output or control parameters of previous trials for generating the input of the current trial. In order to apply the iterative learning controller for a real application and reduce the memory size for implementation, a current error based sampled-data proportional-derivative(PD) type iterative learning controller is proposed for control systems with initial resetting error, input disturbance and output measurement noise in this paper.The proposed iterative learning controller is simple and effective. The first contribution in this paper is to prove the learning error convergence via a rigorous technical analysis. It is shown that the learning error will converge to a residual set if a forgetting factor is introduced in the controller. All the theoretical results are also shown by computer simulations. The second main contribution is to realize the iterative learning controller by a digital circuit using a field programmable gate array(FPGA) chip applied to repetitive position tracking control of direct current(DC) motors. The feasibility and effectiveness of the proposed current error based sampleddata iterative learning controller are demonstrated by the experiment results. Finally, the relationship between learning performance and design parameters are also discussed extensively.