Trigger characteristics of electrostatic discharge(ESD)protecting devices operating under various ambient temperatures ranging from 30℃to 195℃are investigated.The studied ESD protecting devices are the H-gate NMOS t...Trigger characteristics of electrostatic discharge(ESD)protecting devices operating under various ambient temperatures ranging from 30℃to 195℃are investigated.The studied ESD protecting devices are the H-gate NMOS transistors fabricated with a 0.18-μm partially depleted silicon-on-insulator(PDSOI)technology.The measurements are conducted by using a transmission line pulse(TLP)test system.The different temperature-dependent trigger characteristics of groundedgate(GGNMOS)mode and the gate-triggered(GTNMOS)mode are analyzed in detail.The underlying physical mechanisms related to the effect of temperature on the first breakdown voltage V_(T1)investigated through the assist of technology computer-aided design(TCAD)simulation.展开更多
Gate-grounded n-channel metal-oxide-semiconductor(GGNMOS)devices have been widely implemented as power clamps to protect semiconductor devices from electrostatic discharge stress owing to their simple construction,eas...Gate-grounded n-channel metal-oxide-semiconductor(GGNMOS)devices have been widely implemented as power clamps to protect semiconductor devices from electrostatic discharge stress owing to their simple construction,easy triggering,and low power dissipation.We present a novel I-V characterization of the GGNMOS used as the power clamp in complementary metal-oxide-semiconductor circuits as a result of switching the ESD paths under different impact energies.This special effect could cause an unexpected latch-up or pre-failure phenomenon in some applications with relatively large capacitances from power supply to power ground,and thus should be urgently analyzed and resolved.Transmission-linepulse,human-body-modal,and light-emission tests were performed to explore the root cause.展开更多
A novel dual-directional silicon controlled rectifier(DDSCR) device with embedded PNP structure(DDSCR-PNP) is proposed for electrostatic discharge(ESD) protection, which has greatly reduced latch-up risk owing t...A novel dual-directional silicon controlled rectifier(DDSCR) device with embedded PNP structure(DDSCR-PNP) is proposed for electrostatic discharge(ESD) protection, which has greatly reduced latch-up risk owing to the improved holding voltage(V_h/. Firstly, the working mechanism of the DDSCR-PNP is analyzed. The theoretical analysis indicates that the proposed device possesses good voltage clamp ability due to the embedded PNP(PNP_2). Then, experimental devices are fabricated in a 0.35 m bipolar-CMOS-DMOS process and measured with a Barth 4002 transmission line pulse testing system. The results show that the V_h of DDSCR-PNP is much higher than that of the conventional DDSCR, and can be further increased by adjusting the P well width.However, the reduced leakage current(I_L/ of the DDSCR-PNP shows obvious fluctuations when the P well width is increased to more than 12 m. Finally, the factors influencing V_h and I_L are investigated by Sentaurus simulations. The results verify that the lateral PNP_2 helps to increase V_h and decrease I_L. When the P well width is further increased, the effect of the lateral PNP_2 is weakened, causing an increased I_L. The proposed DDSCR-PNP provides an effective and attractive ESD protection solution for high-voltage integrated circuits.展开更多
基金the National Natural Science Foundation of China(Grant No.61804168)。
文摘Trigger characteristics of electrostatic discharge(ESD)protecting devices operating under various ambient temperatures ranging from 30℃to 195℃are investigated.The studied ESD protecting devices are the H-gate NMOS transistors fabricated with a 0.18-μm partially depleted silicon-on-insulator(PDSOI)technology.The measurements are conducted by using a transmission line pulse(TLP)test system.The different temperature-dependent trigger characteristics of groundedgate(GGNMOS)mode and the gate-triggered(GTNMOS)mode are analyzed in detail.The underlying physical mechanisms related to the effect of temperature on the first breakdown voltage V_(T1)investigated through the assist of technology computer-aided design(TCAD)simulation.
基金Project supported by the National Natural Science Foundation of China(Grant No.61974017)。
文摘Gate-grounded n-channel metal-oxide-semiconductor(GGNMOS)devices have been widely implemented as power clamps to protect semiconductor devices from electrostatic discharge stress owing to their simple construction,easy triggering,and low power dissipation.We present a novel I-V characterization of the GGNMOS used as the power clamp in complementary metal-oxide-semiconductor circuits as a result of switching the ESD paths under different impact energies.This special effect could cause an unexpected latch-up or pre-failure phenomenon in some applications with relatively large capacitances from power supply to power ground,and thus should be urgently analyzed and resolved.Transmission-linepulse,human-body-modal,and light-emission tests were performed to explore the root cause.
基金supported by the Fundamental Research Funds for the Central Universities(No.JUSRP51323B)the Joint Innovation Project of Jiangsu Province(No.BY2013015-19)+2 种基金the Summit of the Six Top Talents Program of Jiangsu Province(No.DZXX-053)the Graduate Student Innovation Program for Universities of Jiangsu Province(Nos.KYLX_1119SJZZ_0148)
文摘A novel dual-directional silicon controlled rectifier(DDSCR) device with embedded PNP structure(DDSCR-PNP) is proposed for electrostatic discharge(ESD) protection, which has greatly reduced latch-up risk owing to the improved holding voltage(V_h/. Firstly, the working mechanism of the DDSCR-PNP is analyzed. The theoretical analysis indicates that the proposed device possesses good voltage clamp ability due to the embedded PNP(PNP_2). Then, experimental devices are fabricated in a 0.35 m bipolar-CMOS-DMOS process and measured with a Barth 4002 transmission line pulse testing system. The results show that the V_h of DDSCR-PNP is much higher than that of the conventional DDSCR, and can be further increased by adjusting the P well width.However, the reduced leakage current(I_L/ of the DDSCR-PNP shows obvious fluctuations when the P well width is increased to more than 12 m. Finally, the factors influencing V_h and I_L are investigated by Sentaurus simulations. The results verify that the lateral PNP_2 helps to increase V_h and decrease I_L. When the P well width is further increased, the effect of the lateral PNP_2 is weakened, causing an increased I_L. The proposed DDSCR-PNP provides an effective and attractive ESD protection solution for high-voltage integrated circuits.