In the present work, a two-dimensional（2D） analytical framework of triple material symmetrical gate stack（TMGS）DG-MOSFET is presented in order to subdue the short channel effects. A lightly doped channel along wit...In the present work, a two-dimensional（2D） analytical framework of triple material symmetrical gate stack（TMGS）DG-MOSFET is presented in order to subdue the short channel effects. A lightly doped channel along with triple material gate having different work functions and symmetrical gate stack structure, showcases substantial betterment in quashing short channel effects to a good extent. The device functioning amends in terms of improved exemption to threshold voltage roll-off, thereby suppressing the short channel effects. The encroachments of respective device arguments on the threshold voltage of the proposed structure are examined in detail. The significant outcomes are compared with the numerical simulation data obtained by using 2D ATLAS;device simulator to affirm and formalize the proposed device structure.展开更多
This paper presents a compact two-dimensional analytical device model of surface potential,in addition to electric field of triple-material double-gate(TMDG)tunnel FET.The TMDG TFET device model is developed using a p...This paper presents a compact two-dimensional analytical device model of surface potential,in addition to electric field of triple-material double-gate(TMDG)tunnel FET.The TMDG TFET device model is developed using a parabolic approximation method in the channel depletion space and a boundary state of affairs across the drain and source.The TMDG TFET device is used to analyze the electrical performance of the TMDG structure in terms of changes in potential voltage,lateral and vertical electric field.Because the TMDG TFET has a simple compact structure,the surface potential is computationally efficient and,therefore,may be utilized to analyze and characterize the gate-controlled devices.Furthermore,using Kane's model,the current across the drain can be modeled.The graph results achieved from this device model are close to the data collected from the technology computer aided design(TCAD)simulation.展开更多
A vertically movable gate field effect transistor(VMGFET) is proposed and demonstrated for a microaccelerometer application. The VMGFET using air gap as an insulator layer allows the gate to move on the substrate vert...A vertically movable gate field effect transistor(VMGFET) is proposed and demonstrated for a microaccelerometer application. The VMGFET using air gap as an insulator layer allows the gate to move on the substrate vertically by external forces. Finite element analysis is used to simulate mechanical behaviors of the designed structure. For the simulation, the ground acceleration spectrum of the 1952 Kern County Earthquake is employed to investigate the structural integrity of the sensor in vibration. Based on the simulation, a prototype VMGFET accelerometer is fabricated from silicon on insulator wafer. According to current–voltage characteristics of the prototype VMGFET, the threshold voltage is measured to be 2.32 V, which determines the effective charge density and the mutual transconductance of1.545910-8C cm-2and 6.59 m A V-1, respectively. The device sensitivity is 9.36–9.42 m V g-1in the low frequency,and the first natural frequency is found to be 1230 Hz. The profile smoothness of the sensed signal is in 3 d B range up to1 k Hz.展开更多
Static Random Access Memory(SRAM) based Field Programmable Gate Array(FPGA) is widely applied in the field of aerospace, whose anti-SEU(Single Event Upset) capability becomes more and more important. To improve anti-F...Static Random Access Memory(SRAM) based Field Programmable Gate Array(FPGA) is widely applied in the field of aerospace, whose anti-SEU(Single Event Upset) capability becomes more and more important. To improve anti-FPGA SEU capability, the registers of the circuit netlist are tripled and divided into three categories in this study. By the packing algorithm, the registers of triple modular redundancy are loaded into different configurable logic block. At the same time, the packing algorithm considers the effect of large fan-out nets. The experimental results show that the algorithm successfully realize the packing of the register of Triple Modular Redundancy(TMR). Comparing with Timing Versatile PACKing(TVPACK), the algorithm in this study is able to obtain a 11% reduction of the number of the nets in critical path, and a 12% reduction of the time delay in critical path on average when TMR is not considered. Especially, some critical path delay of circuit can be improved about 33%.展开更多
The luminescence intensity regulation of organic light-emitting transistor(OLED)device can be achieved effectively by the combination of graphene vertical field effect transistor(GVFET)and OLED.In this paper,we fabric...The luminescence intensity regulation of organic light-emitting transistor(OLED)device can be achieved effectively by the combination of graphene vertical field effect transistor(GVFET)and OLED.In this paper,we fabricate and characterize the graphene vertical field-effect transistor with gate dielectric of ion-gel film,confirming that its current switching ratio reaches up to 102.Because of the property of high light transmittance in ion-gel film,the OLED device prepared with graphene/PEDOT:PSS as composite anode exhibits good optical properties.We also prepare the graphene vertical organic light-emitting field effect transistor(GVOLEFET)by the combination of GVFET and graphene OLED,analyzing its electrical and optical properties,and confirming that the luminescence intensity can be significantly changed by regulating the gate voltage.展开更多
A novel silicon carbide gate-controlled bipolar field effect composite transistor with poly silicon region(SiC GCBTP)is proposed.Different from the traditional electrode connection mode of SiC vertical diffused MOS(VD...A novel silicon carbide gate-controlled bipolar field effect composite transistor with poly silicon region(SiC GCBTP)is proposed.Different from the traditional electrode connection mode of SiC vertical diffused MOS(VDMOS),the P+region of P-well is connected with the gate in SiC GCBTP,and the polysilicon region is added between the P+region and the gate.By this method,additional minority carriers can be injected into the drift region at on-state,and the distribution of minority carriers in the drift region will be optimized,so the on-state current is increased.In terms of static characteristics,it has the same high breakdown voltage(811 V)as SiC VDMOS whose length of drift is 5.5μm.The on-state current of SiC GCBTP is 2.47×10^(-3)A/μm(V_(G)=10 V,V_(D)=10 V)which is 5.7 times of that of SiC IGBT and 36.4 times of that of SiC VDMOS.In terms of dynamic characteristics,the turn-on time of SiC GCBTP is only 0.425 ns.And the turn-off time of SiC GCBTP is similar to that of SIC insulated gate bipolar transistor(IGBT),which is 114.72 ns.展开更多
现有分阶段解码的实体关系抽取模型仍存在着阶段间特征融合不充分的问题,会增大曝光偏差对抽取性能的影响。为此,提出一种双关系预测和特征融合的实体关系抽取模型(entity relation extraction model with dual relation prediction and...现有分阶段解码的实体关系抽取模型仍存在着阶段间特征融合不充分的问题,会增大曝光偏差对抽取性能的影响。为此,提出一种双关系预测和特征融合的实体关系抽取模型(entity relation extraction model with dual relation prediction and feature fusion,DRPFF),该模型使用预训练的基于Transformer的双向编码表示模型(bidirectional encoder representation from transformers,BERT)对文本进行编码,并设计两阶段的双关系预测结构来减少抽取过程中错误三元组的生成。在阶段间通过门控线性单元(gated linear unit,GLU)和条件层规范化(conditional layer normalization,CLN)组合的结构来更好地融合实体之间的特征。在NYT和WebNLG这2个公开数据集上的试验结果表明,该模型相较于基线方法取得了更好的效果。展开更多
文摘In the present work, a two-dimensional（2D） analytical framework of triple material symmetrical gate stack（TMGS）DG-MOSFET is presented in order to subdue the short channel effects. A lightly doped channel along with triple material gate having different work functions and symmetrical gate stack structure, showcases substantial betterment in quashing short channel effects to a good extent. The device functioning amends in terms of improved exemption to threshold voltage roll-off, thereby suppressing the short channel effects. The encroachments of respective device arguments on the threshold voltage of the proposed structure are examined in detail. The significant outcomes are compared with the numerical simulation data obtained by using 2D ATLAS;device simulator to affirm and formalize the proposed device structure.
基金supported by Women Scientist Scheme-A, Department of Science and Technology, New Delhi, Government of India, under the Grant SR/WOS-A/ET-5/2017
文摘This paper presents a compact two-dimensional analytical device model of surface potential,in addition to electric field of triple-material double-gate(TMDG)tunnel FET.The TMDG TFET device model is developed using a parabolic approximation method in the channel depletion space and a boundary state of affairs across the drain and source.The TMDG TFET device is used to analyze the electrical performance of the TMDG structure in terms of changes in potential voltage,lateral and vertical electric field.Because the TMDG TFET has a simple compact structure,the surface potential is computationally efficient and,therefore,may be utilized to analyze and characterize the gate-controlled devices.Furthermore,using Kane's model,the current across the drain can be modeled.The graph results achieved from this device model are close to the data collected from the technology computer aided design(TCAD)simulation.
基金supported by the National Research Foundation of Korea(NRF)funded by the Korea government(MSIP)(No.2012M2A8A5025825)
文摘A vertically movable gate field effect transistor(VMGFET) is proposed and demonstrated for a microaccelerometer application. The VMGFET using air gap as an insulator layer allows the gate to move on the substrate vertically by external forces. Finite element analysis is used to simulate mechanical behaviors of the designed structure. For the simulation, the ground acceleration spectrum of the 1952 Kern County Earthquake is employed to investigate the structural integrity of the sensor in vibration. Based on the simulation, a prototype VMGFET accelerometer is fabricated from silicon on insulator wafer. According to current–voltage characteristics of the prototype VMGFET, the threshold voltage is measured to be 2.32 V, which determines the effective charge density and the mutual transconductance of1.545910-8C cm-2and 6.59 m A V-1, respectively. The device sensitivity is 9.36–9.42 m V g-1in the low frequency,and the first natural frequency is found to be 1230 Hz. The profile smoothness of the sensed signal is in 3 d B range up to1 k Hz.
基金Supported by the National Natural Science Foundation of China(No.61106033)
文摘Static Random Access Memory(SRAM) based Field Programmable Gate Array(FPGA) is widely applied in the field of aerospace, whose anti-SEU(Single Event Upset) capability becomes more and more important. To improve anti-FPGA SEU capability, the registers of the circuit netlist are tripled and divided into three categories in this study. By the packing algorithm, the registers of triple modular redundancy are loaded into different configurable logic block. At the same time, the packing algorithm considers the effect of large fan-out nets. The experimental results show that the algorithm successfully realize the packing of the register of Triple Modular Redundancy(TMR). Comparing with Timing Versatile PACKing(TVPACK), the algorithm in this study is able to obtain a 11% reduction of the number of the nets in critical path, and a 12% reduction of the time delay in critical path on average when TMR is not considered. Especially, some critical path delay of circuit can be improved about 33%.
基金Project supported by the National Natural Science Foundation of China(Grant No.31872901)the National Key Research and Development Program of China(Grant No.2016YFA0501602).
文摘The luminescence intensity regulation of organic light-emitting transistor(OLED)device can be achieved effectively by the combination of graphene vertical field effect transistor(GVFET)and OLED.In this paper,we fabricate and characterize the graphene vertical field-effect transistor with gate dielectric of ion-gel film,confirming that its current switching ratio reaches up to 102.Because of the property of high light transmittance in ion-gel film,the OLED device prepared with graphene/PEDOT:PSS as composite anode exhibits good optical properties.We also prepare the graphene vertical organic light-emitting field effect transistor(GVOLEFET)by the combination of GVFET and graphene OLED,analyzing its electrical and optical properties,and confirming that the luminescence intensity can be significantly changed by regulating the gate voltage.
基金Project supported in part by the Science Foundation for Distinguished Young Scholars of Shaanxi Province,China(Grant No.2018JC-017)111 Project(Grant No.B12026)。
文摘A novel silicon carbide gate-controlled bipolar field effect composite transistor with poly silicon region(SiC GCBTP)is proposed.Different from the traditional electrode connection mode of SiC vertical diffused MOS(VDMOS),the P+region of P-well is connected with the gate in SiC GCBTP,and the polysilicon region is added between the P+region and the gate.By this method,additional minority carriers can be injected into the drift region at on-state,and the distribution of minority carriers in the drift region will be optimized,so the on-state current is increased.In terms of static characteristics,it has the same high breakdown voltage(811 V)as SiC VDMOS whose length of drift is 5.5μm.The on-state current of SiC GCBTP is 2.47×10^(-3)A/μm(V_(G)=10 V,V_(D)=10 V)which is 5.7 times of that of SiC IGBT and 36.4 times of that of SiC VDMOS.In terms of dynamic characteristics,the turn-on time of SiC GCBTP is only 0.425 ns.And the turn-off time of SiC GCBTP is similar to that of SIC insulated gate bipolar transistor(IGBT),which is 114.72 ns.
文摘现有分阶段解码的实体关系抽取模型仍存在着阶段间特征融合不充分的问题,会增大曝光偏差对抽取性能的影响。为此,提出一种双关系预测和特征融合的实体关系抽取模型(entity relation extraction model with dual relation prediction and feature fusion,DRPFF),该模型使用预训练的基于Transformer的双向编码表示模型(bidirectional encoder representation from transformers,BERT)对文本进行编码,并设计两阶段的双关系预测结构来减少抽取过程中错误三元组的生成。在阶段间通过门控线性单元(gated linear unit,GLU)和条件层规范化(conditional layer normalization,CLN)组合的结构来更好地融合实体之间的特征。在NYT和WebNLG这2个公开数据集上的试验结果表明,该模型相较于基线方法取得了更好的效果。
