RESEARCH ON THE PACKING ALGORITHM FOR ANTI-SEU OF FPGA BASED ON TRIPLE MODULAR REDUNDANCY AND THE NUMBERS OF FAN-OUTS OF THE NET

Static Random Access Memory(SRAM) based Field Programmable Gate Array(FPGA) is widely applied in the field of aerospace, whose anti-SEU(Single Event Upset) capability becomes more and more important. To improve anti-FPGA SEU capability, the registers of the circuit netlist are tripled and divided into three categories in this study. By the packing algorithm, the registers of triple modular redundancy are loaded into different configurable logic block. At the same time, the packing algorithm considers the effect of large fan-out nets. The experimental results show that the algorithm successfully realize the packing of the register of Triple Modular Redundancy(TMR). Comparing with Timing Versatile PACKing(TVPACK), the algorithm in this study is able to obtain a 11% reduction of the number of the nets in critical path, and a 12% reduction of the time delay in critical path on average when TMR is not considered. Especially, some critical path delay of circuit can be improved about 33%.

A high-level synthesis based dual-module redundancy with multi-residue detection(DMR-MRD)fault-tolerant method for on-board processing satellite communication systems

On board processing(OBP) satellite systems have obtained more and more attentions in recent years because of their high efficiency and performance.However,the OBP transponders are very sensitive to the high energy particles in the space radiation environments.Single event upset(SEU)is one of the major radiation effects,which influences the satellite reliability greatly.Triple modular redundancy(TMR) is a classic and efficient method to mask SEUs.However,TMR uses three identical modules and a comparison logic,the circuit size becomes unacceptable,especially in the resource limited environments such as OBP systems.Considering that,a new SEU-tolerant method based on residue code and high-level synthesis(HLS) is proposed,and the new method is applied to FIR filters,which are typical structures in the OBP systems.The simulation results show that,for an applicable HLS scheduling scheme,area reduction can be reduced by 48.26%compared to TMR,while fault missing rate is 0.15%.

Low complexity SEU mitigation technique for SRAM-based FPGAs

An internal single event upset（SEU）mitigation technique is proposed,which reads back the configuration frames from the static random access memory（SRAM）-based field programmable gate array（FPGA）through an internal port and compares them with those stored in the radiationhardened memory to detect and correct SEUs.Triple modular redundancy（TMR）,which triplicates the circuit of the technique and uses majority voters to isolate any single upset within it,is used to enhance the reliability.Performance analysis shows that the proposed technique can satisfy the requirement of ordinary aerospace missions with less power dissipation,size and weight.The fault injection experiment validates that the proposed technique is capable of correcting most errors to protect spaceborne facilities from SEUs.

Multi-objective Particle Swarm Optimization Algorithm Based on Performance and Reliability of Discrete System Resources Configuration

Considering research on multi-objective optimization for reliability and performance suffering cost constraints in digital circuits,an improved multi-objective optimization algorithm based on performance and reliability was proposed to solve the problem of discrete system resources configuration in this paper. This algorithm used the particle-swarm optimization( PSO) to evaluate the tradeoffs configuration of the system resources between reliability and performance and proved the feasibility through the simulation.Finally, the information of resources configuration from optimization algorithm was used to effectively guide the system design so as to mitigate soft errors caused by single event effect( SEE).

A dual redundancy radiation-hardened flip–flop based on a C-element in a 65 nm process

A radiation-hardened flip-flop is proposed to mitigate the single event upset （SEU） effect. Immunity was achieved through the use of C-elements and redundant storage elements. It takes advantage of the property of a C-element in which it enters a high impedance mode when its inputs are of different logic values. Redundant storage nodes are then used to drive the C-elements so that a single upset pulse in any storage will be prevented from altering the state of the output of the flip-flop. The flip-flop was implemented using 48 transistors and occupied an area of 30.78 μm2, using 65 nm CMOS process. It consumed 22.6% fewer transistors as compared to the traditional SEU resilient TMR flip-flop.

Partial-TMR: A New Method for Protecting Register Files Against Soft Error Based on Lifetime Analysis

High-energy particles in the space can easily cause soft error in register file(RF).As a critical structure in a processor,RF often stores data for long periods of time and is read frequently,resulting in a higher probability of spreading corrupted data to other parts of the processor.The triple modular redundancy(TMR)is a common and effective fault tolerance method that enables multi-bit error correction.Designing full TMR for all the registers could cause excessive area and power overheads.However,some registers in RF have less impact on processor reliability.Therefore,there is no need to design TMR for them.This paper designs an efficient strategy which can rate the registers in RF based on their vulnerability.Based on the proposed strategy,a new RF fault tolerance method named Partial-TMR formulates in this paper,which selectively protects more vulnerable registers against multi-bit error,and improves fault tolerance efficiency.For integer RF,Partial-TMR improves its soft error correction capability by 24.5%relative to the baseline system and 3%relative to ParShield,while for floating-point RF,the improvement comes to 5.17%and 0.58%respectively.The soft error correction capability of Partial-TMR is slightly lower than that of full TMR by 1%to 3%,but Partial-TMR significantly cuts the area and power overheads.Compared with full TMR,Partial-TMR decreases the area and power overheads by 71.6%and 64.9%,respectively.It also has little impact on the performance.Partial-TMR is a more cost-effective fault tolerance method compared with ParShield and full TMR.