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RESEARCH ON THE PACKING ALGORITHM FOR ANTI-SEU OF FPGA BASED ON TRIPLE MODULAR REDUNDANCY AND THE NUMBERS OF FAN-OUTS OF THE NET
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作者 Cui Xiuhai Yang Haigang +1 位作者 Peng Yu Peng Xiyuan 《Journal of Electronics(China)》 2014年第4期284-289,共6页
Static Random Access Memory(SRAM) based Field Programmable Gate Array(FPGA) is widely applied in the field of aerospace, whose anti-SEU(Single Event Upset) capability becomes more and more important. To improve anti-F... Static Random Access Memory(SRAM) based Field Programmable Gate Array(FPGA) is widely applied in the field of aerospace, whose anti-SEU(Single Event Upset) capability becomes more and more important. To improve anti-FPGA SEU capability, the registers of the circuit netlist are tripled and divided into three categories in this study. By the packing algorithm, the registers of triple modular redundancy are loaded into different configurable logic block. At the same time, the packing algorithm considers the effect of large fan-out nets. The experimental results show that the algorithm successfully realize the packing of the register of Triple Modular Redundancy(TMR). Comparing with Timing Versatile PACKing(TVPACK), the algorithm in this study is able to obtain a 11% reduction of the number of the nets in critical path, and a 12% reduction of the time delay in critical path on average when TMR is not considered. Especially, some critical path delay of circuit can be improved about 33%. 展开更多
关键词 Field Programmable Gate Array (FPGA) triple Modular Redundancy (TMR) Packing algorithm Fan-outs of the net Critical path delayCLC number:TN473
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Design and Reliability Analysis of DP-3 Dynamic Positioning Control Architecture 被引量:4
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作者 王芳 万磊 +1 位作者 姜大鹏 徐玉如 《China Ocean Engineering》 SCIE EI 2011年第4期709-720,共12页
As the exploration and exploitation of oil and gas proliferate throughout deepwater area, the requirements on the reliability of dynamic positioning system become increasingly stringent. The control objective ensuring... As the exploration and exploitation of oil and gas proliferate throughout deepwater area, the requirements on the reliability of dynamic positioning system become increasingly stringent. The control objective ensuring safety operation at deep water will not be met by a single controller for dynamic positioning. In order to increase the availability and reliability of dynamic positioning control system, the triple redundancy hardware and software control architectures were designed and developed according to the safe specifications of DP-3 classification notation for dynamically positioned ships and rigs. The hardware redundant configuration takes the form of triple-redundant hot standby configuration including three identical operator stations and three real-time control computers which connect each other through dual networks. The function of motion control and redundancy management of control computers were implemented by software on the real-time operating system VxWorks. The software realization of task loose synchronization, majority voting and fault detection were presented in details. A hierarchical software architecture was planed during the development of software, consisting of application layer, real-time layer and physical layer. The behavior of the DP-3 dynamic positioning control system was modeled by a Markov model to analyze its reliability. The effects of variation in parameters on the reliability measures were investigated. The time domain dynamic simulation was carried out on a deepwater drilling rig to prove the feasibility of the proposed control architecture 展开更多
关键词 DP-3 dynamic positioning system reliability triple redundancy motion control redundancy management
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Low complexity SEU mitigation technique for SRAM-based FPGAs
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作者 JIANG Run-zhen WANG Yong-qing +1 位作者 FENG Zhi-qiang YU Xiu-li 《Journal of Beijing Institute of Technology》 EI CAS 2016年第3期403-412,共10页
An internal single event upset(SEU)mitigation technique is proposed,which reads back the configuration frames from the static random access memory(SRAM)-based field programmable gate array(FPGA)through an intern... An internal single event upset(SEU)mitigation technique is proposed,which reads back the configuration frames from the static random access memory(SRAM)-based field programmable gate array(FPGA)through an internal port and compares them with those stored in the radiationhardened memory to detect and correct SEUs.Triple modular redundancy(TMR),which triplicates the circuit of the technique and uses majority voters to isolate any single upset within it,is used to enhance the reliability.Performance analysis shows that the proposed technique can satisfy the requirement of ordinary aerospace missions with less power dissipation,size and weight.The fault injection experiment validates that the proposed technique is capable of correcting most errors to protect spaceborne facilities from SEUs. 展开更多
关键词 static random access memory (SRAM) field programmable gate array (FPGA) single event upset (SEU) low complexity triple modular redundancy SCRUBBING
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Multi-objective Particle Swarm Optimization Algorithm Based on Performance and Reliability of Discrete System Resources Configuration
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作者 周国财 高翔 《Journal of Donghua University(English Edition)》 EI CAS 2014年第6期850-852,共3页
Considering research on multi-objective optimization for reliability and performance suffering cost constraints in digital circuits,an improved multi-objective optimization algorithm based on performance and reliabili... Considering research on multi-objective optimization for reliability and performance suffering cost constraints in digital circuits,an improved multi-objective optimization algorithm based on performance and reliability was proposed to solve the problem of discrete system resources configuration in this paper. This algorithm used the particle-swarm optimization( PSO) to evaluate the tradeoffs configuration of the system resources between reliability and performance and proved the feasibility through the simulation.Finally, the information of resources configuration from optimization algorithm was used to effectively guide the system design so as to mitigate soft errors caused by single event effect( SEE). 展开更多
关键词 multi-objective optimization function module soft error triple modular redundancy(TMR)
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A high-level synthesis based dual-module redundancy with multi-residue detection(DMR-MRD)fault-tolerant method for on-board processing satellite communication systems
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作者 杨文慧 Chen Xiang +2 位作者 Wang Yu Zhao Ming Wang Jing 《High Technology Letters》 EI CAS 2014年第3期245-252,共8页
On board processing(OBP) satellite systems have obtained more and more attentions in recent years because of their high efficiency and performance.However,the OBP transponders are very sensitive to the high energy par... On board processing(OBP) satellite systems have obtained more and more attentions in recent years because of their high efficiency and performance.However,the OBP transponders are very sensitive to the high energy particles in the space radiation environments.Single event upset(SEU)is one of the major radiation effects,which influences the satellite reliability greatly.Triple modular redundancy(TMR) is a classic and efficient method to mask SEUs.However,TMR uses three identical modules and a comparison logic,the circuit size becomes unacceptable,especially in the resource limited environments such as OBP systems.Considering that,a new SEU-tolerant method based on residue code and high-level synthesis(HLS) is proposed,and the new method is applied to FIR filters,which are typical structures in the OBP systems.The simulation results show that,for an applicable HLS scheduling scheme,area reduction can be reduced by 48.26%compared to TMR,while fault missing rate is 0.15%. 展开更多
关键词 single event upset (SEU) residue code triple modular redundancy (TMR) high-level synthesis (HLS) fault missing rate
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Architecture design for reliable and reconfigurable FPGA-based GNC computer for deep space exploration 被引量:11
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作者 YANG MengFei LIU Bo +6 位作者 GONG Jian LIU HongJin HU HongKai DONG YangYang SHI Lei ZHAO YunFu MIAO ZhiFu 《Science China(Technological Sciences)》 SCIE EI CAS CSCD 2016年第2期289-300,共12页
SRAM(static random access memory)-based FPGA(field programmable gate array), owing to its large capacity, high performance, and dynamical reconfiguration, has become an attractive platform for So PC(system on programm... SRAM(static random access memory)-based FPGA(field programmable gate array), owing to its large capacity, high performance, and dynamical reconfiguration, has become an attractive platform for So PC(system on programmable chip) development. However, as the configuration memory and logic memory of the SRAM-based FPGA are highly susceptible to SEUs(single-event upsets) in deep space, it is a challenge to design and implement a highly reliable FPGA-based system for spacecraft, and no practical architecture has been proposed. In this paper, a new architecture for a reliable and reconfigurable FPGAbased computer in a highly critical GNC(guidance navigation and control) system is proposed. To mitigate the effect of an SEU on the system, multi-layer reconfiguration and multi-layer TMR(triple module redundancy) techniques are proposed, with a reliable reconfigurable real-time operating system(Space OS) managing the system level fault tolerance of the computer in the architecture. The proposed architecture for the reconfigurable FPGA-based computer has been implemented with COTS(commercial off the shelf) FPGA and has firstly been applied to the GNC system of a circumlunar return and reentry flight vehicle. The in-orbit results show that the proposed architecture is capable of meeting the requirements of high reliability and high availability, and can provide the expressive varying functionality and runtime flexibility for an FPGA-based GNC computer in deep space. 展开更多
关键词 fault tolerance system on programmable chip (SoPC) field programmable gate array (FPGA) multi-layer triple mod-ule redundancy intelligence reconfiguration
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Partial-TMR: A New Method for Protecting Register Files Against Soft Error Based on Lifetime Analysis 被引量:1
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作者 Xian-Geng Liang Ying-Ke Gao Geng-Xin Hua 《Journal of Computer Science & Technology》 SCIE EI CSCD 2021年第5期1089-1101,共13页
High-energy particles in the space can easily cause soft error in register file(RF).As a critical structure in a processor,RF often stores data for long periods of time and is read frequently,resulting in a higher pro... High-energy particles in the space can easily cause soft error in register file(RF).As a critical structure in a processor,RF often stores data for long periods of time and is read frequently,resulting in a higher probability of spreading corrupted data to other parts of the processor.The triple modular redundancy(TMR)is a common and effective fault tolerance method that enables multi-bit error correction.Designing full TMR for all the registers could cause excessive area and power overheads.However,some registers in RF have less impact on processor reliability.Therefore,there is no need to design TMR for them.This paper designs an efficient strategy which can rate the registers in RF based on their vulnerability.Based on the proposed strategy,a new RF fault tolerance method named Partial-TMR formulates in this paper,which selectively protects more vulnerable registers against multi-bit error,and improves fault tolerance efficiency.For integer RF,Partial-TMR improves its soft error correction capability by 24.5%relative to the baseline system and 3%relative to ParShield,while for floating-point RF,the improvement comes to 5.17%and 0.58%respectively.The soft error correction capability of Partial-TMR is slightly lower than that of full TMR by 1%to 3%,but Partial-TMR significantly cuts the area and power overheads.Compared with full TMR,Partial-TMR decreases the area and power overheads by 71.6%and 64.9%,respectively.It also has little impact on the performance.Partial-TMR is a more cost-effective fault tolerance method compared with ParShield and full TMR. 展开更多
关键词 register file soft error lifetime analysis selective protection triple modular redundancy(TMR)
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A dual redundancy radiation-hardened flip–flop based on a C-element in a 65 nm process
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作者 陈刚 高博 龚敏 《Journal of Semiconductors》 EI CAS CSCD 2013年第9期160-163,共4页
A radiation-hardened flip-flop is proposed to mitigate the single event upset (SEU) effect. Immunity was achieved through the use of C-elements and redundant storage elements. It takes advantage of the property of a... A radiation-hardened flip-flop is proposed to mitigate the single event upset (SEU) effect. Immunity was achieved through the use of C-elements and redundant storage elements. It takes advantage of the property of a C-element in which it enters a high impedance mode when its inputs are of different logic values. Redundant storage nodes are then used to drive the C-elements so that a single upset pulse in any storage will be prevented from altering the state of the output of the flip-flop. The flip-flop was implemented using 48 transistors and occupied an area of 30.78 μm2, using 65 nm CMOS process. It consumed 22.6% fewer transistors as compared to the traditional SEU resilient TMR flip-flop. 展开更多
关键词 single event effect radiation hardening by design triple modular redundancy flip-flop C-element
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