In signal processing and communication systems,digital filters are widely employed.In some circumstances,the reliability of those systems is crucial,necessitating the use of fault tolerant filter implementations.Many ...In signal processing and communication systems,digital filters are widely employed.In some circumstances,the reliability of those systems is crucial,necessitating the use of fault tolerant filter implementations.Many strategies have been presented throughout the years to achieve fault tolerance by utilising the structure and properties of the filters.As technology advances,more complicated systems with several filters become possible.Some of the filters in those complicated systems frequently function in parallel,for example,by applying the same filter to various input signals.Recently,a simple strategy for achieving fault tolerance that takes advantage of the availability of parallel filters was given.Many fault-tolerant ways that take advantage of the filter’s structure and properties have been proposed throughout the years.The primary idea is to use structured authentication scan chains to study the internal states of finite impulse response(FIR)components in order to detect and recover the exact state of faulty modules through the state of non-faulty modules.Finally,a simple solution of Double modular redundancy(DMR)based fault tolerance was developed that takes advantage of the availability of parallel filters for image denoising.This approach is expanded in this short to display how parallel filters can be protected using error correction codes(ECCs)in which each filter is comparable to a bit in a standard ECC.“Advanced error recovery for parallel systems,”the suggested technique,can find and eliminate hidden defects in FIR modules,and also restore the system from multiple failures impacting two FIR modules.From the implementation,Xilinx ISE 14.7 was found to have given significant error reduction capability in the fault calculations and reduction in the area which reduces the cost of implementation.Faults were introduced in all the outputs of the functional filters and found that the fault in every output is corrected.展开更多
Static Random Access Memory(SRAM) based Field Programmable Gate Array(FPGA) is widely applied in the field of aerospace, whose anti-SEU(Single Event Upset) capability becomes more and more important. To improve anti-F...Static Random Access Memory(SRAM) based Field Programmable Gate Array(FPGA) is widely applied in the field of aerospace, whose anti-SEU(Single Event Upset) capability becomes more and more important. To improve anti-FPGA SEU capability, the registers of the circuit netlist are tripled and divided into three categories in this study. By the packing algorithm, the registers of triple modular redundancy are loaded into different configurable logic block. At the same time, the packing algorithm considers the effect of large fan-out nets. The experimental results show that the algorithm successfully realize the packing of the register of Triple Modular Redundancy(TMR). Comparing with Timing Versatile PACKing(TVPACK), the algorithm in this study is able to obtain a 11% reduction of the number of the nets in critical path, and a 12% reduction of the time delay in critical path on average when TMR is not considered. Especially, some critical path delay of circuit can be improved about 33%.展开更多
On board processing(OBP) satellite systems have obtained more and more attentions in recent years because of their high efficiency and performance.However,the OBP transponders are very sensitive to the high energy par...On board processing(OBP) satellite systems have obtained more and more attentions in recent years because of their high efficiency and performance.However,the OBP transponders are very sensitive to the high energy particles in the space radiation environments.Single event upset(SEU)is one of the major radiation effects,which influences the satellite reliability greatly.Triple modular redundancy(TMR) is a classic and efficient method to mask SEUs.However,TMR uses three identical modules and a comparison logic,the circuit size becomes unacceptable,especially in the resource limited environments such as OBP systems.Considering that,a new SEU-tolerant method based on residue code and high-level synthesis(HLS) is proposed,and the new method is applied to FIR filters,which are typical structures in the OBP systems.The simulation results show that,for an applicable HLS scheduling scheme,area reduction can be reduced by 48.26%compared to TMR,while fault missing rate is 0.15%.展开更多
This paper proposes a checkpoint rollback strategy for real-time systems with double modular redundancy.Without built-in fault-detection and spare processors,our scheme is able to recover from both transient and perma...This paper proposes a checkpoint rollback strategy for real-time systems with double modular redundancy.Without built-in fault-detection and spare processors,our scheme is able to recover from both transient and permanent faults.Two comparisons are conducted at each checkpoint.First,the states stored in two consecutive checkpoints of one processor are compared for checking integrity of the processor.The states of two processors are also compared for detecting faults and the system rolls back to the previous checkpoint whenever required by logic of the proposed scheme.A Markov model is induced by the fault recovery scheme and analyzed to provide the probability of task completion within its deadline.The optimal number of checkpoints is selected so as to maximize the probability of task completion.展开更多
文摘In signal processing and communication systems,digital filters are widely employed.In some circumstances,the reliability of those systems is crucial,necessitating the use of fault tolerant filter implementations.Many strategies have been presented throughout the years to achieve fault tolerance by utilising the structure and properties of the filters.As technology advances,more complicated systems with several filters become possible.Some of the filters in those complicated systems frequently function in parallel,for example,by applying the same filter to various input signals.Recently,a simple strategy for achieving fault tolerance that takes advantage of the availability of parallel filters was given.Many fault-tolerant ways that take advantage of the filter’s structure and properties have been proposed throughout the years.The primary idea is to use structured authentication scan chains to study the internal states of finite impulse response(FIR)components in order to detect and recover the exact state of faulty modules through the state of non-faulty modules.Finally,a simple solution of Double modular redundancy(DMR)based fault tolerance was developed that takes advantage of the availability of parallel filters for image denoising.This approach is expanded in this short to display how parallel filters can be protected using error correction codes(ECCs)in which each filter is comparable to a bit in a standard ECC.“Advanced error recovery for parallel systems,”the suggested technique,can find and eliminate hidden defects in FIR modules,and also restore the system from multiple failures impacting two FIR modules.From the implementation,Xilinx ISE 14.7 was found to have given significant error reduction capability in the fault calculations and reduction in the area which reduces the cost of implementation.Faults were introduced in all the outputs of the functional filters and found that the fault in every output is corrected.
基金Supported by the National Natural Science Foundation of China(No.61106033)
文摘Static Random Access Memory(SRAM) based Field Programmable Gate Array(FPGA) is widely applied in the field of aerospace, whose anti-SEU(Single Event Upset) capability becomes more and more important. To improve anti-FPGA SEU capability, the registers of the circuit netlist are tripled and divided into three categories in this study. By the packing algorithm, the registers of triple modular redundancy are loaded into different configurable logic block. At the same time, the packing algorithm considers the effect of large fan-out nets. The experimental results show that the algorithm successfully realize the packing of the register of Triple Modular Redundancy(TMR). Comparing with Timing Versatile PACKing(TVPACK), the algorithm in this study is able to obtain a 11% reduction of the number of the nets in critical path, and a 12% reduction of the time delay in critical path on average when TMR is not considered. Especially, some critical path delay of circuit can be improved about 33%.
基金Supported by the National S&T Major Project(No.2011ZX03003-003-01,2011ZX03004-004)the National Basic Research Program of China(No.2012CB316002)
文摘On board processing(OBP) satellite systems have obtained more and more attentions in recent years because of their high efficiency and performance.However,the OBP transponders are very sensitive to the high energy particles in the space radiation environments.Single event upset(SEU)is one of the major radiation effects,which influences the satellite reliability greatly.Triple modular redundancy(TMR) is a classic and efficient method to mask SEUs.However,TMR uses three identical modules and a comparison logic,the circuit size becomes unacceptable,especially in the resource limited environments such as OBP systems.Considering that,a new SEU-tolerant method based on residue code and high-level synthesis(HLS) is proposed,and the new method is applied to FIR filters,which are typical structures in the OBP systems.The simulation results show that,for an applicable HLS scheduling scheme,area reduction can be reduced by 48.26%compared to TMR,while fault missing rate is 0.15%.
文摘This paper proposes a checkpoint rollback strategy for real-time systems with double modular redundancy.Without built-in fault-detection and spare processors,our scheme is able to recover from both transient and permanent faults.Two comparisons are conducted at each checkpoint.First,the states stored in two consecutive checkpoints of one processor are compared for checking integrity of the processor.The states of two processors are also compared for detecting faults and the system rolls back to the previous checkpoint whenever required by logic of the proposed scheme.A Markov model is induced by the fault recovery scheme and analyzed to provide the probability of task completion within its deadline.The optimal number of checkpoints is selected so as to maximize the probability of task completion.
