设计了一款采用硅基板作为载体的毫米波上变频微系统系统级封装(System in Package,SiP)模块。该模块利用类同轴硅通孔(Through-Silicon-Via,TSV)结构解决了毫米波频段信号在转接板层间低损耗垂直传输的问题。该结构整体采用四层硅基板...设计了一款采用硅基板作为载体的毫米波上变频微系统系统级封装(System in Package,SiP)模块。该模块利用类同轴硅通孔(Through-Silicon-Via,TSV)结构解决了毫米波频段信号在转接板层间低损耗垂直传输的问题。该结构整体采用四层硅基板封装,并在封装完成后对硅基射频SiP模块进行了测试。测试结果显示,在工作频段29~31 GHz之间,其增益大于27 dB,端口驻波小于1.4,且带外杂散抑制大于55 dB。该毫米波硅基SiP模块具有结构简单、集成度高、射频性能良好等优点,其体积不到传统二维集成结构的5%,实现了毫米波频段模块的微系统化,可广泛运用于射频微系统。展开更多
A ball grid array （BGA） package based on Si interposer with through silicon via （TSV） was de- signed. Thermal behaviors of the designed BGA with Si interposer has been analyzed and compared to a conventional BGA w...A ball grid array （BGA） package based on Si interposer with through silicon via （TSV） was de- signed. Thermal behaviors of the designed BGA with Si interposer has been analyzed and compared to a conventional BGA with BT substrate in the approach of finite element modeling （FEM）. The Si interposer with TSV was then fabricated and the designed BGA package was demonstrated. The designed BGA pack- age includes a 100 ~m thick Si interposer, which has redistribution copper traces on both sides. Through vias with 25 to 40 ~m diameter were fabricated on the Si interposer using deep reactive ion etching （DRIE）, plasma enhanced chemical vapor deposition （PECVD）, copper electroplating and chemical mechanical pol- ishing （CMP）, etc. TSV in the designed interposer is used as electrical interconnections and cooling chan- nels. 5 mm by 5 mm and 10 mm by 10 mm thermal chips were assembled on the Si interposer.展开更多
Interposers with through-silicon vias(TSVs)play a key role in the three-dimensional integration and packaging of integrated circuits and microelectromechanical systems.In the current practice of fabricating interposer...Interposers with through-silicon vias(TSVs)play a key role in the three-dimensional integration and packaging of integrated circuits and microelectromechanical systems.In the current practice of fabricating interposers,solder balls are placed next to the vias;however,this approach requires a large foot print for the input/output(I/O)connections.Therefore,in this study,we investigate the possibility of placing the solder balls directly on top of the vias,thereby enabling a smaller pitch between the solder balls and an increased density of the I/O connections.To reach this goal,inkjet printing(that is,piezo and super inkjet)was used to successfully fill and planarize hollow metal TSVs with a dielectric polymer.The under bump metallization(UBM)pads were also successfully printed with inkjet technology on top of the polymer-filled vias,using either Ag or Au inks.The reliability of the TSV interposers was investigated by a temperature cycling stress test(−40℃ to+125℃).The stress test showed no impact on DC resistance of the TSVs;however,shrinkage and delamination of the polymer was observed,along with some micro-cracks in the UBM pads.For proof of concept,SnAgCu-based solder balls were jetted on the UBM pads.展开更多
An interposer test vehicle with TSVs（through-silicon vias） and two redistribute layers（RDLs） on the top side for 2.5D integration was fabricated and high-frequency interconnections were designed in the form of cop...An interposer test vehicle with TSVs（through-silicon vias） and two redistribute layers（RDLs） on the top side for 2.5D integration was fabricated and high-frequency interconnections were designed in the form of coplanar waveguide（CPW） and micro strip line（MSL） structures. The signal transmission structures were modeled and simulated in a 3D EM tool to estimate the S-parameters. The measurements were carried out using the vector network analyzer（VNA）. The simulated results of the transmission lines on the surface of the interposer without TSVs showed good agreement with the simulated results, while the transmission structures with TSVs showed significant offset between simulation and test results. The parameters of the transmission structures were changed,and the results were also presented and discussed in this paper.展开更多
System-in-packaging(Si P) can realize the integration and miniaturization of electronic devices and it is significant to continue Moore’s law.Through-X-via(TXV) technology is the cornerstone of 3 D-SiP,which enables ...System-in-packaging(Si P) can realize the integration and miniaturization of electronic devices and it is significant to continue Moore’s law.Through-X-via(TXV) technology is the cornerstone of 3 D-SiP,which enables the vertical stacking and electrical interconnection of electronic devices.TXV originated from through-hole(TH) in PCB substrates and evolved in different substrate materials,such as silicon,glass,ceramic,and polymer.This work provides a comprehensive review of four distinguishing TXV technologies(through silicon via(TSV),through glass via(TGV),through ceramic via(TCV),and through mold via(TMV)),including the fabrication mechanisms,processes,and applications.Every TXV technology has unique characteristics and owns particular processes and functions.The process methods,key technologies,application fields,and advantages and disadvantages of each TXV technology were discussed.The cutting-edge through-hole process and development direction were reviewed.展开更多
基金Supported by the National S&T Major Project (No. 2009ZX02038)the National High-Tech Research and Development (863) Program of China (No. 2009AA04321)supported by Cisco Systems Inc
文摘A ball grid array （BGA） package based on Si interposer with through silicon via （TSV） was de- signed. Thermal behaviors of the designed BGA with Si interposer has been analyzed and compared to a conventional BGA with BT substrate in the approach of finite element modeling （FEM）. The Si interposer with TSV was then fabricated and the designed BGA package was demonstrated. The designed BGA pack- age includes a 100 ~m thick Si interposer, which has redistribution copper traces on both sides. Through vias with 25 to 40 ~m diameter were fabricated on the Si interposer using deep reactive ion etching （DRIE）, plasma enhanced chemical vapor deposition （PECVD）, copper electroplating and chemical mechanical pol- ishing （CMP）, etc. TSV in the designed interposer is used as electrical interconnections and cooling chan- nels. 5 mm by 5 mm and 10 mm by 10 mm thermal chips were assembled on the Si interposer.
基金This work is supported by ENIAC-JU Project Prominent Grant No 324189 and Tekes Grant No.40336/12 and Vinnova Grants Nos.2012-04301,2012-04287,and 2012-04314MM is supported by the Academy of Finland Grant Nos.288945 and 294119The work of Silex and KTH was funded in part through an Industrial Ph.D.grant from the Swedish Foundation for Strategic Research(SSF),Grant No.ID14-0033.
文摘Interposers with through-silicon vias(TSVs)play a key role in the three-dimensional integration and packaging of integrated circuits and microelectromechanical systems.In the current practice of fabricating interposers,solder balls are placed next to the vias;however,this approach requires a large foot print for the input/output(I/O)connections.Therefore,in this study,we investigate the possibility of placing the solder balls directly on top of the vias,thereby enabling a smaller pitch between the solder balls and an increased density of the I/O connections.To reach this goal,inkjet printing(that is,piezo and super inkjet)was used to successfully fill and planarize hollow metal TSVs with a dielectric polymer.The under bump metallization(UBM)pads were also successfully printed with inkjet technology on top of the polymer-filled vias,using either Ag or Au inks.The reliability of the TSV interposers was investigated by a temperature cycling stress test(−40℃ to+125℃).The stress test showed no impact on DC resistance of the TSVs;however,shrinkage and delamination of the polymer was observed,along with some micro-cracks in the UBM pads.For proof of concept,SnAgCu-based solder balls were jetted on the UBM pads.
基金Project supported by the National S&T Major Projects(No.2011ZX02709)the National Natural Science Foundation of China(No.61176098)support from the 100 Talents Program of The Chinese Academy of Sciences
文摘An interposer test vehicle with TSVs（through-silicon vias） and two redistribute layers（RDLs） on the top side for 2.5D integration was fabricated and high-frequency interconnections were designed in the form of coplanar waveguide（CPW） and micro strip line（MSL） structures. The signal transmission structures were modeled and simulated in a 3D EM tool to estimate the S-parameters. The measurements were carried out using the vector network analyzer（VNA）. The simulated results of the transmission lines on the surface of the interposer without TSVs showed good agreement with the simulated results, while the transmission structures with TSVs showed significant offset between simulation and test results. The parameters of the transmission structures were changed,and the results were also presented and discussed in this paper.
基金supported by the Aerospace S&T Group Application Innovation Program Project(No:09428ADA)the Key Research and Development Project of Hubei Province(Grant Nos.2020BAB068 and 2021BAA071)。
文摘System-in-packaging(Si P) can realize the integration and miniaturization of electronic devices and it is significant to continue Moore’s law.Through-X-via(TXV) technology is the cornerstone of 3 D-SiP,which enables the vertical stacking and electrical interconnection of electronic devices.TXV originated from through-hole(TH) in PCB substrates and evolved in different substrate materials,such as silicon,glass,ceramic,and polymer.This work provides a comprehensive review of four distinguishing TXV technologies(through silicon via(TSV),through glass via(TGV),through ceramic via(TCV),and through mold via(TMV)),including the fabrication mechanisms,processes,and applications.Every TXV technology has unique characteristics and owns particular processes and functions.The process methods,key technologies,application fields,and advantages and disadvantages of each TXV technology were discussed.The cutting-edge through-hole process and development direction were reviewed.
