Si–Ge based vertical tunnel field-effect transistor of junction-less structure with improved sensitivity using dielectric modulation for biosensing applications

A dielectric modulation strategy for gate oxide material that enhances the sensing performance of biosensors in junction-less vertical tunnel field effect transistors(TFETs)is reported.The junction-less technique,in which metals with specific work functions are deposited on the source region to modulate the channel conductivity,is used to provide the necessary doping for the proper functioning of the device.TCAD simulation studies of the proposed structure and junction structure have been compared,and showed an enhanced rectification of 10^(4) times.The proposed structure is designed to have a nanocavity of length 10 nm on the left-and right-hand sides of the fixed gate dielectric,which improves the biosensor capture area,and hence the sensitivity.By considering neutral and charged biomolecules with different dielectric constants,TCAD simulation studies were compared for their sensitivities.The off-state current IOFFcan be used as a suitable sensing parameter because it has been observed that the proposed sensor exhibits a significant variation in drain current.Additionally,it has been investigated how positively and negatively charged biomolecules affect the drain current and threshold voltage.To explore the device performance when the nanogaps are fully filled,half filled and unevenly filled,extensive TCAD simulations have been run.The proposed TFET structure is further benchmarked to other structures to show its better sensing capabilities.

Impact of low/high-κ spacer-source overlap on characteristics of tunnel dielectric based tunnel field-effect transistor

The effects of low-κ and high-κ spacer were investigated on the novel tunnel dielectric based tunnel field-effect transistor(TD-FET) mainly based upon ultra-thin dielectric direct tunneling mechanism. Drive currents consist of direct tunneling current and band-to-band tunneling(BTBT) current. Meanwhile, tunneling position of the TD-FET differs from conventional tunnel-FET in which the electron and hole tunneling occur at intermediate rather than surface in channel(or source-channel junction under gate dielectric). The 2-D nature of TD-FET current flow is also discussed that the on-current is degraded with an increase in the spacer width. BTBT current will not begin to play part in tunneling current until gate voltage is 0.2 V. We clearly identify the influence of the tunneling dielectric layer and spacer electrostatic field on the device characteristics by numerical simulations. The inserted Si_3N_4 tunnel layer between P+ region and N+ region can significantly shorten the direct and band-to-band tunneling path, so a reduced subthreshold slope(Ss) and a high on-current can be achieved. Above all the ambipolar current is effectively suppressed, thus reducing off-current. TD-FET demonstrates excellent performance for low-power applications.

Influence of trap-assisted tunneling on trap-assisted tunneling current in double gate tunnel field-effect transistor

Trap-assisted tunneling（TAT） has attracted more and more attention, because it seriously affects the sub-threshold characteristic of tunnel field-effect transistor（TFET）. In this paper, we assess subthreshold performance of double gate TFET（DG-TFET） through a band-to-band tunneling（BTBT） model, including phonon-assisted scattering and acoustic surface phonons scattering. Interface state density profile（D_（it）） and the trap level are included in the simulation to analyze their effects on TAT current and the mechanism of gate leakage current.

Ge/Si heterojunction L-shape tunnel field-effect transistors with hetero-gate-dielectric

A Ge/Si heterojunction L-shaped tunnel field-effect transistor combined with hetero-gate-dielectric （GHL-TFET） is proposed and investigated by TCAD simulation. Current-voltage characteristics, energy-band diagrams, and the distri- bution of the band-to-band tunneling （BTBT） generation rate of GHL-TFET are analyzed. In addition, the effect of the vertical channel width on the ON-current is studied and the thickness of the gate dielectric is optimized for better suppression of ambipolar current. Moreover, analog/RF figure-of-merits of GHL-TFET are also investigated in terms of the cut-off frequency and gain bandwidth production. Simulation results indicate that the ON-current of GHL-TFET is increased by about three orders of magnitude compared with that of the conventional L-shaped TFET. Besides, the introduction of the hetero-gate-dielectric not only suppresses the ambipolar current effectively but also improves the analog/RF performance drastically. It is demonstrated that the maximum cut-off frequency of GHL-TFET is about 160 GHz, which is 20 times higher than that of the conventional L-shaped TFET.

Heteromaterial-gate line tunnel field-effect transistor based on Si/Ge heterojunction

A Si/Ge heterojunction line tunnel field-effect transistor （LTFET） with a symmetric heteromaterial gate is proposed. Compared to single-material-gate LTFETs, the heteromaterial gate LTFET shows an off-state leakage current that is three orders of magnitude lower, and steeper subthreshold characteristics, without degradation in the on-state current. We reveal that these improvements are due to the induced local potential barrier, which arises from the energy-band profile modulation effect. Based on this novel structure, the impacts of the physical parameters of the gap region between the pocket and the drain, including the work-function mismatch between the pocket gate and the gap gate, the type of dopant, and the doping concentration, on the device performance are investigated. Simulation and theoretical calculation results indicate that the gap gate material and n-type doping level in the gap region should be optimized simultaneously to make this region fully depleted for further suppression of the off-state leakage current.

Characteristic enhancement in tunnel field-effect transistors via introduction of vertical graded source

A novel vertical graded source tunnel field-effect transistor(VGS-TFET)is proposed to improve device performance.By introducing a source with linearly graded component,the on-state current increases by more than two decades higher than that of the conventional GaAs TFETs without sacrificing the subthreshold swing(SS)due to the improved band-to-band tunneling efficiency.Compared with the conventional TFETs,much larger drive current range can be achieved by the proposed VGS-TFET with SS below the thermionic limitation of 60 mV/dec.Furthermore,the minimum SS about 20 mV/dec indicates its promising potential for further ultralow power applications.

Optimization of ambipolar current and analog/RF performance for T-shaped tunnel field-effect transistor with gate dielectric spacer

A new T-shaped tunnel field-effect transistor(TTFET) with gate dielectric spacer(GDS) structure is proposed in this paper. To further studied the effects of GDS structure on the TTFET, detailed device characteristics such as current-voltage relationships, energy band diagrams, band-to-band tunneling(BTBT) rate and the magnitude of the electric field are investigated by using TCAD simulation. It is found that compared with conventional TTFET and TTFET with gate-drain overlap(GDO) structure, GDS-TTFET not only has the minimum ambipolar current but also can suppress the ambipolar current under a more extensive bias range. Furthermore, the analog/RF performances of GDS-TTFET are also investigated in terms of transconductance, gate-source capacitance, gate-drain capacitance, cutoff frequency, and gain bandwidth production. By inserting a low-κ spacer layer between the gate electrode and the gate dielectric, the GDS structure can effectively reduce parasitic capacitances between the gate and the source/drain, which leads to better performance in term of cutoff frequency and gain bandwidth production. Finally, the thickness of the gate dielectric spacer is optimized for better ambipolar current suppression and improved analog/RF performance.

Double-gate tunnel field-effect transistor:Gate threshold voltage modeling and extraction

The tunnel field-effect transistor(TFET) is a potential candidate for the post-CMOS era.As one of the most important electrical parameters of a device,double gate TFET(DG-TFET) gate threshold voltage was studied.First,a numerical simulation study of transfer characteristic and gate threshold voltage in DG-TFET was reported.Then,a simple analytical model for DG-TFET gate threshold voltage VTG was built by solving quasi-two-dimensional Poisson equation in Si film.The model as a function of the drain voltage,the Si layer thickness,the gate length and the gate dielectric was discussed.It is shown that the proposed model is consistent with the simulation results.This model should be useful for further investigation of performance of circuits containing TFETs.

Double-gate-all-around tunnel field-effect transistor

In this work, a double-gate-all-around tunneling field-effect transistor is proposed. The performance of the novel device is studied by numerical simulation. The results show that with a thinner body and an additional core gate, the novel device achieves a steeper subthreshold slope, less susceptibility to the short channel effect, higher on-state current, and larger on/off current ratio than the traditional gate-all-around tunneling field-effect transistor. The excellent performance makes the proposed structure more attractive to further dimension scaling.

Effect of external magnetic field on the instability of THz plasma waves in nanoscale graphene field-effect transistors

The instability of plasma waves in the channel of field-effect transistors will cause the electromagnetic waves with THz frequency.Based on a self-consistent quantum hydrodynamic model,the instability of THz plasmas waves in the channel of graphene field-effect transistors has been investigated with external magnetic field and quantum effects.We analyzed the influence of weak magnetic fields,quantum effects,device size,and temperature on the instability of plasma waves under asymmetric boundary conditions numerically.The results show that the magnetic fields,quantum effects,and the thickness of the dielectric layer between the gate and the channel can increase the radiation frequency.Additionally,we observed that increase in temperature leads to a decrease in both oscillation frequency and instability increment.The numerical results and accompanying images obtained from our simulations provide support for the above conclusions.

A non-quasi-static model for nanowire gate-all-around tunneling field-effect transistors

Nanowires with gate-all-around(GAA) structures are widely considered as the most promising candidate for 3-nm technology with the best ability of suppressing the short channel effects,and tunneling field effect transistors(TFETs)based on GAA structures also present improved performance.In this paper,a non-quasi-static(NQS) device model is developed for nanowire GAA TFETs.The model can predict the transient current and capacitance varying with operation frequency,which is beyond the ability of the quasi-static(QS) model published before.Excellent agreements between the model results and numerical simulations are obtained.Moreover,the NQS model is derived from the published QS model including the current-voltage(I-V) and capacitance-voltage(C-V) characteristics.Therefore,the NQS model is compatible with the QS model for giving comprehensive understanding of GAA TFETs and would be helpful for further study of TFET circuits based on nanowire GAA structure.

High on-state current p-type tunnel effect transistor based on doping modulation

To solve the problem of the low on-state current in p-type tunnel field-effect transistors(p-TFETs),this paper analyzes the mechanism of adjusting the tunneling current of a TFET device determined by studying the influence of the peak position of ion implantation on the potential of the p-TFET device surface and the width of the tunneling barrier.Doping-regulated silicon-based high on-state p-TFET devices are designed and fabricated,and the test results show that the on-state current of the fabricated devices can be increased by about two orders of magnitude compared with the current of other devices with the same structure.This method provides a new idea for the realization of high on-state current TFET devices.

Two-dimensional threshold voltage model of a nanoscale silicon-on-insulator tunneling field-effect transistor

The tunneling field-effect transistor（TFET） is a potential candidate for the post-CMOS era.In this paper,a threshold voltage model is developed for this new kind of device.First,two-dimensional（2D） models are used to describe the distributions of potential and electric field in the channel and two depletion regions.Then based on the physical definition of threshold voltage for the nanoscale TFET,the threshold voltage model is developed.The accuracy of the proposed model is verified by comparing the calculated results with the 2D device simulation data.It has been demonstrated that the effects of varying the device parameters can easily be investigated using the model presented in this paper.This threshold voltage model provides a valuable reference to TFET device design,simulation,and fabrication.

A 2-D semi-analytical model of double-gate tunnel field-effect transistor

A 2-D semi-analytical model of double gate （DG） tunneling field-effect transistor （TFET） is proposed. By aid of introducing two rectangular sources located in the gate dielectric layer and the channel, the 2-D Poisson equation is solved by using a semi-analytical method combined with an eigenfunction expansion method. The expression of the surface potential is obtained, which is a special function for the infinite series expressions. The influence of the mobile charges on the potential profile is taken into account in the proposed model. On the basis of the potential profile, the shortest tunneling length and the average electrical field can be derived, and the drain current is then constructed by using Kane＇s model. In particular, the changes of the tunneling parameters Ak and Bk influenced by the drain-source voltage are also incorporated in the predicted model. The proposed model shows a good agreement with TCAD simulation results under different drain-source voltages, silicon film thicknesses, gate dielectric layer thicknesses, and gate dielectric layer constants. Therefore, it is useful to optimize the DG TFET and this provides a physical insight for circuit level design.

Novel GaN-based double-channel p-heterostructure field-effect transistors with a p-GaN insertion layer

GaN-based p-channel heterostructure field-effect transistors(p-HFETs)face significant constraints on on-state currents compared with n-channel high electron mobility transistors.In this work,we propose a novel double heterostructure which introduces an additional p-GaN insertion layer into traditional p-HFETs.The impact of the device structure on the hole densities and valence band energies of both the upper and lower channels is analyzed by using Silvaco TACD simulations,including the thickness of the upper AlGaN layer and the doping impurities and concentration in the GaN buffer layer,as well as the thickness and Mg-doping concentration in the p-GaN insertion layer.With the help of the p-GaN insertion layer,the C-doping concentration in the GaN buffer layer can be reduced,while the density of the two-dimensional hole gas in the lower channel is enhanced at the same time.This work suggests that a double heterostructure with a p-GaN insertion layer is a better approach to improve p-HFETs compared with those devices with C-doped buffer layer alone.

Ge Complementary Tunneling Field-Effect Transistors Featuring Dopant Segregated NiGe Source/Drain

Ge complementary tunneling field-effect transistors（TFETs） are fabricated with the NiGe metal source/drain（S/D） structure. The dopant segregation method is employed to form the NiGe/Ge tunneling junctions of sufficiently high Schottky barrier heights. As a result, the Ge p-and n-TFETs exhibit decent electrical properties of large ON-state current and steep sub-threshold slope（S factor）. Especially, I_d of 0.2 μA/μm is revealed at V_g-V_（th） = V_d = ±0.5 V for Ge pTFETs,with the S factor of 28 mV/dec at 7 K.

Design and Analysis of Graphene Based Tunnel Field Effect Transistor with Various Ambipolar Reducing Techniques

The fundamental advantages of carbon-based graphene material,such as its high tunnelling probability,symmetric band structure(linear dependence of the energy band on the wave direction),low effective mass,and characteristics of its 2D atomic layers,are the main focus of this research work.The impact of channel thickness,gate under-lap,asymmetric source/drain doping method,workfunction of gate contact,and High-K material on Graphene-based Tunnel Field Effect Transistor(TFET)is analyzed with 20 nm technology.Physical modelling and electrical characteristic performance have been simulated using the Atlas device simulator of SILVACO TCAD with user-defined material syntax for the newly included graphene material in comparison to silicon carbide(SiC).The simulation results in significant suppression of ambipolar current to voltage characteristics of TFET and modelled device exhibits a significant improvement in subthreshold swing(0.0159 V/decade),the ratio of Ion/Ioff(1000),and threshold voltage(-0.2 V with highly doped p-type source and 0.2 V with highly doped n-type drain)with power supply of 0.5 V,which make it useful for low power digital applications.

Effect of spin on the instability of THz plasma waves in field-effect transistors under non-ideal boundary conditions

Terahertz(THz) radiation can be generated due to the instability of THz plasma waves in field-effect transistors(FETs). In this work, we discuss the instability of THz plasma waves in the channel of FETs with spin and quantum effects under non-ideal boundary conditions. We obtain a linear dispersion relation by using the hydrodynamic equation, Maxwell equation and spin equation. The influence of source capacitance, drain capacitance, spin effects, quantum effects and channel width on the instability of THz plasma waves under the non-ideal boundary conditions is investigated in great detail. The results of numerical simulation show that the THz plasma wave is unstable when the drain capacitance is smaller than the source capacitance;the oscillation frequency with asymmetric boundary conditions is smaller than that under non-ideal boundary conditions;the instability gain of THz plasma waves becomes lower under non-ideal boundary conditions. This finding provides a new idea for finding efficient THz radiation sources and opens up a new mechanism for the development of THz technology.

Characteristics of cylindrical surrounding-gate GaAs_xSb_(1-x)/In_yGa_(1-y)As heterojunction tunneling field-effect transistors

A Ⅲ-Ⅴ heterojunction tunneling field-effect transistor(TFET) can enhance the on-state current effectively,and GaAsSb/InGaAs heterojunction exhibits better performance with the adjustable band alignment by modulating the alloy composition.In this paper,the performance of the cylindrical surrounding-gate GaAsSb/InGaAs heterojunction TFET with gate-drain underlap is investigated by numerical simulation.We validate that reducing drain doping concentration and increasing gate-drain underlap could be effective ways to reduce the off-state current and subthreshold swing(SS),while increasing source doping concentration and adjusting the composition of GaAsSbInGaAs can improve the on-state current.In addition,the resonant TFET based on GaAsSb/InGaAs is also studied,and the result shows that the minimum and average of SS reach 11 mV/decade and 20 mV/decade for five decades of drain current,respectively,and is much superior to the conventional TFET.

An accurate analytical surface potential model of heterojunction tunnel FET

Based on the accurate and efficient thermal injection method, we develop a fully analytical surface potential model for the heterojunction tunnel field-effect transistor(H-TFET). This model accounts for both the effects of source depletion and inversion charge, which are the key factors influencing the charge, capacitance and current in H-TFET. The accuracy of the model is validated against TCAD simulation and is greatly improved in comparison with the conventional model based on Maxwell–Boltzmann approximation. Furthermore, the dependences of the surface potential and electric field on biases are well predicted and thoroughly analyzed.