Gate-to-body tunneling current model for silicon-on-insulator MOSFETs

A gate-to-body tunneling current model for silicon-on-insulator （SOl） devices is simulated. As verified by the mea- sured data, the model, considering both gate voltage and drain voltage dependence as well as image force-induced barrier low effect, provides a better prediction of the tunneling current and gate-induced floating body effect than the BSIMSOI4 model. A delayed gate-induced floating body effect is also predicted by the model.

Characteristics of cylindrical surrounding-gate GaAs_xSb_(1-x)/In_yGa_(1-y)As heterojunction tunneling field-effect transistors

A Ⅲ-Ⅴ heterojunction tunneling field-effect transistor(TFET) can enhance the on-state current effectively,and GaAsSb/InGaAs heterojunction exhibits better performance with the adjustable band alignment by modulating the alloy composition.In this paper,the performance of the cylindrical surrounding-gate GaAsSb/InGaAs heterojunction TFET with gate-drain underlap is investigated by numerical simulation.We validate that reducing drain doping concentration and increasing gate-drain underlap could be effective ways to reduce the off-state current and subthreshold swing(SS),while increasing source doping concentration and adjusting the composition of GaAsSbInGaAs can improve the on-state current.In addition,the resonant TFET based on GaAsSb/InGaAs is also studied,and the result shows that the minimum and average of SS reach 11 mV/decade and 20 mV/decade for five decades of drain current,respectively,and is much superior to the conventional TFET.

Double-gate tunnel field-effect transistor:Gate threshold voltage modeling and extraction

The tunnel field-effect transistor(TFET) is a potential candidate for the post-CMOS era.As one of the most important electrical parameters of a device,double gate TFET(DG-TFET) gate threshold voltage was studied.First,a numerical simulation study of transfer characteristic and gate threshold voltage in DG-TFET was reported.Then,a simple analytical model for DG-TFET gate threshold voltage VTG was built by solving quasi-two-dimensional Poisson equation in Si film.The model as a function of the drain voltage,the Si layer thickness,the gate length and the gate dielectric was discussed.It is shown that the proposed model is consistent with the simulation results.This model should be useful for further investigation of performance of circuits containing TFETs.

Heteromaterial-gate line tunnel field-effect transistor based on Si/Ge heterojunction

A Si/Ge heterojunction line tunnel field-effect transistor （LTFET） with a symmetric heteromaterial gate is proposed. Compared to single-material-gate LTFETs, the heteromaterial gate LTFET shows an off-state leakage current that is three orders of magnitude lower, and steeper subthreshold characteristics, without degradation in the on-state current. We reveal that these improvements are due to the induced local potential barrier, which arises from the energy-band profile modulation effect. Based on this novel structure, the impacts of the physical parameters of the gap region between the pocket and the drain, including the work-function mismatch between the pocket gate and the gap gate, the type of dopant, and the doping concentration, on the device performance are investigated. Simulation and theoretical calculation results indicate that the gap gate material and n-type doping level in the gap region should be optimized simultaneously to make this region fully depleted for further suppression of the off-state leakage current.

Optimization of ambipolar current and analog/RF performance for T-shaped tunnel field-effect transistor with gate dielectric spacer

A new T-shaped tunnel field-effect transistor(TTFET) with gate dielectric spacer(GDS) structure is proposed in this paper. To further studied the effects of GDS structure on the TTFET, detailed device characteristics such as current-voltage relationships, energy band diagrams, band-to-band tunneling(BTBT) rate and the magnitude of the electric field are investigated by using TCAD simulation. It is found that compared with conventional TTFET and TTFET with gate-drain overlap(GDO) structure, GDS-TTFET not only has the minimum ambipolar current but also can suppress the ambipolar current under a more extensive bias range. Furthermore, the analog/RF performances of GDS-TTFET are also investigated in terms of transconductance, gate-source capacitance, gate-drain capacitance, cutoff frequency, and gain bandwidth production. By inserting a low-κ spacer layer between the gate electrode and the gate dielectric, the GDS structure can effectively reduce parasitic capacitances between the gate and the source/drain, which leads to better performance in term of cutoff frequency and gain bandwidth production. Finally, the thickness of the gate dielectric spacer is optimized for better ambipolar current suppression and improved analog/RF performance.

An analytic model for gate-all-around silicon nanowire tunneling field effect transistors

An analytical model of gate-all-around （GAA） silicon nanowire tunneling field effect transistors （NW-TFETs） is developted based on the surface potential solutions in the channel direction and considering the band to band tunneling （BTBT） efficiency. The three-dimensional Poisson equation is solved to obtain the surface potential distributions in the partition regions along the channel direction for the NW-TFET, and a tunneling current model using Kane＇s expression is developed. The validity of the developed model is shown by the good agreement between the model predictions and the TCAD simulation results.

Double-gate-all-around tunnel field-effect transistor

In this work, a double-gate-all-around tunneling field-effect transistor is proposed. The performance of the novel device is studied by numerical simulation. The results show that with a thinner body and an additional core gate, the novel device achieves a steeper subthreshold slope, less susceptibility to the short channel effect, higher on-state current, and larger on/off current ratio than the traditional gate-all-around tunneling field-effect transistor. The excellent performance makes the proposed structure more attractive to further dimension scaling.

Ge/Si heterojunction L-shape tunnel field-effect transistors with hetero-gate-dielectric

A Ge/Si heterojunction L-shaped tunnel field-effect transistor combined with hetero-gate-dielectric （GHL-TFET） is proposed and investigated by TCAD simulation. Current-voltage characteristics, energy-band diagrams, and the distri- bution of the band-to-band tunneling （BTBT） generation rate of GHL-TFET are analyzed. In addition, the effect of the vertical channel width on the ON-current is studied and the thickness of the gate dielectric is optimized for better suppression of ambipolar current. Moreover, analog/RF figure-of-merits of GHL-TFET are also investigated in terms of the cut-off frequency and gain bandwidth production. Simulation results indicate that the ON-current of GHL-TFET is increased by about three orders of magnitude compared with that of the conventional L-shaped TFET. Besides, the introduction of the hetero-gate-dielectric not only suppresses the ambipolar current effectively but also improves the analog/RF performance drastically. It is demonstrated that the maximum cut-off frequency of GHL-TFET is about 160 GHz, which is 20 times higher than that of the conventional L-shaped TFET.

基于深度学习的盾构机土舱压力场预测方法

土舱压力是盾构机受力状态和掌子面稳定等核心问题中的关键因素。土舱压力具有显著的空间变异性,其形成演化机制源于装备与岩土之间的复杂耦合作用,与地质特征、掘进参数等多源参数相关。然而,现有土舱压力预测方法一般未考虑空间分布特征或地质参数影响。针对该问题,提出了一种基于空间分布物理特征函数导引深度学习的盾构机土舱压力场预测方法。该方法构建物理特征函数用于解耦土舱压力空间分布特征,采用卷积神经网络和门控循环单元分别提取多源参数历史信息的空间特征和特征系数的时序特征,结合多源参数实时信息对特征系数进行预测,从而实现土舱压力场的预测。以长沙地铁四号线某区段为案例,利用该方法准确预测了土舱压力空间分布实测数据,准确率高达0.98,验证了所提方法的有效性。敏感性分析表明,不同地层中土舱压力空间分布特征系数的主要敏感参数基本一致,但其敏感度随地层地质条件的变化规律差异显著,可为复杂地层盾构机土舱压力精细化调控提供参考。

CrCl_(3)隧穿磁阻的界面效应与多场效应调控

磁隧道结是研究磁性材料自旋结构、输运特性、磁相变和磁各向异性的重要实验平台.本研究基于干法转移技术制备了以机械剥离的少层范德瓦耳斯反铁磁绝缘体三氯化铬(CrCl_(3))为势垒层、少层石墨烯为电极的磁隧道结原型器件结构,并进行了低温电磁输运测量,除观测到自旋过滤效应引起的隧穿磁阻外,还发现多种由非传统效应引起的磁阻变化.基于对隧道结自旋结构和能带结构的分析,本文将之归因于由磁近邻效应引起的隧穿机制改变,以及石墨烯电极态密度在高磁场下出现的量子振荡行为.本文报道了在二维磁隧道结中与隧穿磁阻相关且此前未被广泛关注的物理现象,加深了对此类二维异质结构中载流子输运特性的理解,为二维磁性材料的物理性质研究及其自旋电子学应用拓展了新的途径.

某水电站泄洪洞工作闸门室弧门支撑梁结构受力及配筋研究

某水电站左岸山体内平行布置3条泄洪洞,有压洞与无压洞衔接部位设工作闸门室连通3条泄洪洞,闸门室底部采用弧形工作门控制水流,弧门支撑大梁布置于工作闸门室洞挖后的反坡段。弧门支撑大梁断面较大,属大体积混凝土结构,施工期受温度荷载作用,与反坡段岩体接触关系多变,联合受力问题复杂。为此,采用FLAC~(3D)软件,考虑运行期各设计状况及荷载效应组合,重点分析了闸门室支撑梁结构与围岩形成联合承载特性,并据此开展支撑梁结构内力计算、结构配筋设计。研究成果可为其他类似工程泄洪洞闸门室弧门支撑梁配筋提供参考。

多批次预制的内河沉管隧道干坞坞口封闭方案研究

为优化多批次预制的内河沉管隧道干坞坞口封闭方案,以广州某典型软土地基中的沉管隧道干坞工程为背景,提出一种半重力式坞门墩+钢坞门的坞口封闭方案,并将其与围堰方案进行了经济合理性比较。通过建立三维有限元模型,分析地连墙接头类型、墙体厚度、坞门墩平面长度等敏感性因素,揭示了格构式地连墙坞门墩的受力机制。研究结果表明:对于多批次预制的内河沉管隧道,半重力式坞门墩+钢坞门坞口封闭方案的造价比围堰方案降低20%以上,且缩短了半年以上的工期;坞门墩格构式地连墙呈现以水平向受力为主的双向板受力特征;刚性接头坞门墩整体性好,柔性接头坞门墩在墙顶盖板的约束下也具有较好的整体性,但二者的位移、弯矩大小和形状均存在差异;随着墙体厚度的增加,墙体的位移减小,弯矩增大;随着坞门墩平面长度的增加,墙体的位移减小,弯矩减小。

异质栅介质双栅隧穿场效应晶体管TCAD仿真研究

采用异质栅介质结构,加入高k介质Pocket区,对双栅隧穿场效应晶体管进行了改进。通过搭建不同模型,分析了栅介质的长度、介电常数以及Pocket区厚度等参数对器件开态电流Ion、双极性特性、亚阈值摆幅等的影响。TACD仿真结果表明,Ion随介电常数的增大可提升至5.17×10-5A/μm,且双极性电流也有极大的增幅,亚阈值摆幅因开态电流的改善降低至28.3 mV/dec,而异质栅介质的不同长度对器件性能并无明显影响;在双极性上,Pocket区厚度的增加使得栅漏隧穿宽度增大,双极性电流减小至1.0×10-17A/μm,抑制了双极性导通,同时对器件其他特性未产生明显影响。

The conduction mechanism of stress induced leakage current through ultra-thin gate oxide under constant voltage stresses

The conduction mechanism of stress induced leakage current （SILC） through 2nm gate oxide is studied over a gate voltage range between 1.7V and stress voltage under constant voltage stress （CVS）. The simulation results show that the SILC is formed by trap-assisted tunnelling （TAT） process which is dominated by oxide traps induced by high field stresses. Their energy levels obtained by this work are approximately 1.9eV from the oxide conduction band, and the traps are believed to be the oxygen-related donor-like defects induced by high field stresses. The dependence of the trap density on stress time and oxide electric field is also investigated.

闸门开度对泄洪排沙隧洞水力特性影响研究

为揭示闸门开度对泄洪排沙隧洞水力特性的影响规律,建立了不同闸门开度下的排沙隧洞二维模型,采用VOF法和标准κ-ε紊流模型对泄洪排沙隧洞易磨蚀断面流场进行三维数值模拟计算,获得了闸门附近的流态、流速、压强等水力特性,并对比分析了不同闸门开度下的水力特性,得到了闸门处至挑坎之前的空化数。结果表明,当闸门小于1/2最大开度运行时,闸门开度越大,隧洞水流流态越平顺,临底流速过渡越平顺,且隧洞底板上下游压力差越小;闸门开度越小,有压洞内流速越小,容易造成泥沙淤积;闸门开度越大,对隧洞整体运行越有利。研究结果对水工隧洞闸门的运行开度优化及闸门底坎抗磨修复具有指导意义。

Two-dimensional threshold voltage model of a nanoscale silicon-on-insulator tunneling field-effect transistor

The tunneling field-effect transistor（TFET） is a potential candidate for the post-CMOS era.In this paper,a threshold voltage model is developed for this new kind of device.First,two-dimensional（2D） models are used to describe the distributions of potential and electric field in the channel and two depletion regions.Then based on the physical definition of threshold voltage for the nanoscale TFET,the threshold voltage model is developed.The accuracy of the proposed model is verified by comparing the calculated results with the 2D device simulation data.It has been demonstrated that the effects of varying the device parameters can easily be investigated using the model presented in this paper.This threshold voltage model provides a valuable reference to TFET device design,simulation,and fabrication.

Effects of back gate bias on radio-frequency performance in partially depleted silicon-on-inslator nMOSFETs

The effects of back gate bias(BGEs) on radio-frequency(RF) performances in PD SOI n MOSFETs are presented in this paper. Floating body(FB) device, T-gate body-contact(TB) device, and tunnel diode body-contact(TDBC) device, of which the supply voltages are all 1.2 V, are compared under different back gate biases by different figures of merit, such as cut-off frequency( fT), maximum frequency of oscillation( fmax), etc. Because of the lack of a back gate conducting channel, the drain conductance(gd) of TDBC transistor shows a smaller degradation than those of the others, and the trans-conductance(gm) of TDBC is almost independent of back gate bias. The values of fT of TDBC are also kept nearly constant under different back gate biases. However, RF performances of FB and TB each show a significant degradation when the back gate bias is larger than ～ 20 V. The results indicate that TDBC structures could effectively improve the back gate bias in RF performance.

Investigation of gate oxide traps effect on NAND flash memory by TCAD simulation

The effects of gate oxide traps on gate leakage current and device performance of metal–oxide–nitride–oxide–silicon(MONOS)-structured NAND flash memory are investigated through Sentaurus TCAD. The trap-assisted tunneling(TAT)model is implemented to simulate the leakage current of MONOS-structured memory cell. In this study, trap position, trap density, and trap energy are systematically analyzed for ascertaining their influences on gate leakage current, program/erase speed, and data retention properties. The results show that the traps in blocking layer significantly enhance the gate leakage current and also facilitates the cell program/erase. Trap density ~10^(18) cm^(-3) and trap energy ~ 1 eV in blocking layer can considerably improve cell program/erase speed without deteriorating data retention. The result conduces to understanding the role of gate oxide traps in cell degradation of MONOS-structured NAND flash memory.

Gate leakage current of NMOSFET with ultra-thin gate oxide

As dimensions of the metal-oxide-semiconductor field-effect transistor (MOSFET) are scaling down and the thickness of gate oxide is decreased,the gate leakage becomes more and more prominent and has been one of the most important limiting factors to MOSFET and circuits lifetime.Based on reliability theory and experiments,the direct tunneling current in lightly-doped drain (LDD) NMOSFET with 1.4 nm gate oxide fabricated by 90 nm complementary metal oxide semiconductor (CMOS) process was studied in depth.High-precision semiconductor parameter analyzer was used to conduct the tests.Law of variation of the direct tunneling (DT) current with channel length,channel width,measuring voltage,drain bias and reverse substrate bias was revealed.The results show that the change of the DT current obeys index law;there is a linear relationship between gate current and channel dimension;drain bias and substrate bias can reduce the gate current.

Analysis of non-uniform hetero-gate-dielectric dual-material control gate TFET for suppressing ambipolar nature and improving radio-frequency performance

A tunnel field-effect transistor(TFET) is proposed by combining various advantages together, such as non-uniform gate-oxide layer, hetero-gate-dielectric(HGD), and dual-material control-gate(DMCG) technology. The effects of the length of non-uniform gate-oxide layer and dual-material control-gate on the on-state, off-state, and ambipolar currents are investigated. In addition, radio-frequency performance is studied in terms of gain bandwidth product, cut-off frequency,transit time, and transconductance frequency product. Moreover, the length of non-uniform gate-oxide layer and dualmaterial control-gate are optimized to improve the on-off current ratio and radio-frequency performances as well as the suppression of ambipolar current. All results demonstrate that the proposed device not only suppresses ambipolar current but also improves radio-frequency performance compared with the conventional DMCG TFET, which makes the proposed device a better application prospect in the advanced integrated circuits.