The electronic properties and transport properties of MoTe2/SnS2 heterostructure Tunneling FETs are investigated by the density functional theory coupled with non-equilibrium Green’s function method.Two dimensional(2...The electronic properties and transport properties of MoTe2/SnS2 heterostructure Tunneling FETs are investigated by the density functional theory coupled with non-equilibrium Green’s function method.Two dimensional(2D)monolayer MoTe2 and SnS2 are combined to a vertical van der Waals heterojunction.A small staggered band gap is formed in the overlap region,while larger gaps remain in the underlap source and drain regions of monolayer MoTe2 and SnS2 respectively.Such a type-II heterojunction is favorable for tunneling FET.Furthermore,we suggest short stack length and large gate-to-drain overlap to enhance the on-state current suppress the leakage current respectively.The numerical results show that at a low drain to source voltage Vds=0.05V,On/Off current ratio can reach 108 and the On-state currents is over 20μA/μm for ntype devices.Our results present that van der Waals heterostructure TFETs can be potential candidate as next generation ultra-steep subthreshold and low-power electronic applications.展开更多
研究了一种新型非对称栅隧穿场效应晶体管(AG-TFET),新型结构结合了隧穿场效应晶体管陡峭的亚阈值摆幅与无结器件较大的开态电流的优点,其总电流大小受控于底部沟道势垒和p+区与本征沟道区形成的反偏p-i隧穿结处的带隙宽度以及电场强度...研究了一种新型非对称栅隧穿场效应晶体管(AG-TFET),新型结构结合了隧穿场效应晶体管陡峭的亚阈值摆幅与无结器件较大的开态电流的优点,其总电流大小受控于底部沟道势垒和p+区与本征沟道区形成的反偏p-i隧穿结处的带隙宽度以及电场强度。使用Silvaco TCAD软件对器件性能进行了仿真,并对p+区厚度以及底栅栅介质二氧化铪的长度进行了优化。仿真结果表明:新型AG-TFET具有良好的电学特性,在室温下开关电流比可以达到3.3×1010,开态电流为302μA/μm,陡峭的亚阈值摆幅即点亚阈值摆幅为35 m V/dec,平均亚阈值摆幅为54 m V/dec。因此,该新型AG-TFET有望被应用在未来低功耗电路中。展开更多
本文讨论了非硅微电子学,即在硅衬底上利用非硅沟道材料实现互补型金属氧化物半导体(Complememaw Metal Oxide Semiconductor,CMOS)集成电路的微电子科学与技术.文章重点综述了高迁移率锗与锗锡沟道金属氧化物半导体场效应晶体管(Metal ...本文讨论了非硅微电子学,即在硅衬底上利用非硅沟道材料实现互补型金属氧化物半导体(Complememaw Metal Oxide Semiconductor,CMOS)集成电路的微电子科学与技术.文章重点综述了高迁移率锗与锗锡沟道金属氧化物半导体场效应晶体管(Metal Oxide Semiconductor Field Effect Transistor,MOSFET)以及隧穿场效应晶体管(Tunneling Field Effect Transistor,TFET)的研究进展.锗与锗锡具有比硅(Si)材料高的空穴和电子迁移率且容易实现硅衬底集成,是实现高迁移率沟道CMOS器件的理想备选材料.通过调节锡组分,锗锡材料可实现直接带隙结构,从而获得较高的带间隧穿几率,理论和实验证明可用锗锡实现高性能TFET器件.本文具体分析了锗锡MOSFETs和TFETs器件在材料生长、表面钝化、栅叠层、源漏工程、应变工程及器件可靠性等关键问题.展开更多
This paper presents the impact of parameter fluctuation due to process variation on radio frequency （RF） stability performance of double gate tunnel FET （DG TFET）. The influence of parameter fluctuation due to pro...This paper presents the impact of parameter fluctuation due to process variation on radio frequency （RF） stability performance of double gate tunnel FET （DG TFET）. The influence of parameter fluctuation due to process variation leads to DG TFET performance degradation. The RF figures of merit （FoM） such as cut-off frequency （ft）, maximum oscillation frequency （fmax） along with stability factor for different silicon body thickness, gate oxide thickness and gate contact alignment are obtained from extracted device parameters through numerical simulation. The impact of parameter fluctuation of silicon body thickness, gate oxide thickness and gate contact alignment was found significant and the result provides design guidelines ofDG TFET for RF applications.展开更多
In this paper,RF performance analysis of In As-based double gate（DG）tunnel field effect transistors（TFETs）is investigated in both qualitative and quantitative fashion.This investigation is carried out by varying t...In this paper,RF performance analysis of In As-based double gate（DG）tunnel field effect transistors（TFETs）is investigated in both qualitative and quantitative fashion.This investigation is carried out by varying the geometrical and doping parameters of TFETs to extract various RF parameters,unity gain cut-off frequency（f_t）,maximum oscillation frequency（f_（max））,intrinsic gain and admittance（Y）parameters.An asymmetric gate oxide is introduced in the gate-drain overlap and compared with that of DG TFETs.Higher ON-current（ION）of about 0.2 mA and less leakage current（IOFF）of 29 f A is achieved for DG TFET with gate-drain overlap.Due to increase in transconductance（g_m）,higher ft and intrinsic gain is attained for DG TFET with gate-drain overlap.Higher f_（max） of 985 GHz is obtained for drain doping of 5×10^（17）cm^（-3） because of the reduced gate-drain capacitance（C_（gd））with DG TFET with gate-drain overlap.In terms of Y-parameters,gate oxide thickness variation offers better performance due to the reduced values of Cgd.A second order numerical polynomial model is generated for all the RF responses as a function of geometrical and doping parameters.The simulation results are compared with this numerical model where the predicted values match with the simulated values.展开更多
A double-gate tunnel field-effect transistor （DG tunnel FET） has been designed and investigated for various channel materials such as silicon （Si）, gallium arsenide （GaAs）, alminium gallium arsenide （A1xGa1-xAs...A double-gate tunnel field-effect transistor （DG tunnel FET） has been designed and investigated for various channel materials such as silicon （Si）, gallium arsenide （GaAs）, alminium gallium arsenide （A1xGa1-xAs） and CNT using a nano ViDES Device and TCAD SILVACO ATLAS simulator. The proposed devices are com- pared on the basis of inverse subthreshold slope （SS）, ION/IoFF current ratio and leakage current. Using Si as the channel material limits the property to reduce leakage current with scaling of channel, whereas the A1xGa1-xAs based DG tunnel FET provides a better ION/IOFF current ratio （2.51 × 10^6） as compared to other devices keeping the leakage current within permissible limits. The performed silmulation of the CNT based channel in the double-gate tunnel field-effect transistor using the nano ViDES shows better performace for a sub-threshold slope of 29.4 mV/dec as the channel is scaled down. The proposed work shows the potential of the CNT channel based DG tunnel FET as a futuristic device for better switching and high retention time, which makes it suitable for memory based circuits.展开更多
基金the Training Program of the Major Research Plan of the National Natural Science Foundation of China(61774168,91964103)and the MOST(2016YFA0202300).
文摘The electronic properties and transport properties of MoTe2/SnS2 heterostructure Tunneling FETs are investigated by the density functional theory coupled with non-equilibrium Green’s function method.Two dimensional(2D)monolayer MoTe2 and SnS2 are combined to a vertical van der Waals heterojunction.A small staggered band gap is formed in the overlap region,while larger gaps remain in the underlap source and drain regions of monolayer MoTe2 and SnS2 respectively.Such a type-II heterojunction is favorable for tunneling FET.Furthermore,we suggest short stack length and large gate-to-drain overlap to enhance the on-state current suppress the leakage current respectively.The numerical results show that at a low drain to source voltage Vds=0.05V,On/Off current ratio can reach 108 and the On-state currents is over 20μA/μm for ntype devices.Our results present that van der Waals heterostructure TFETs can be potential candidate as next generation ultra-steep subthreshold and low-power electronic applications.
文摘研究了一种新型非对称栅隧穿场效应晶体管(AG-TFET),新型结构结合了隧穿场效应晶体管陡峭的亚阈值摆幅与无结器件较大的开态电流的优点,其总电流大小受控于底部沟道势垒和p+区与本征沟道区形成的反偏p-i隧穿结处的带隙宽度以及电场强度。使用Silvaco TCAD软件对器件性能进行了仿真,并对p+区厚度以及底栅栅介质二氧化铪的长度进行了优化。仿真结果表明:新型AG-TFET具有良好的电学特性,在室温下开关电流比可以达到3.3×1010,开态电流为302μA/μm,陡峭的亚阈值摆幅即点亚阈值摆幅为35 m V/dec,平均亚阈值摆幅为54 m V/dec。因此,该新型AG-TFET有望被应用在未来低功耗电路中。
文摘本文讨论了非硅微电子学,即在硅衬底上利用非硅沟道材料实现互补型金属氧化物半导体(Complememaw Metal Oxide Semiconductor,CMOS)集成电路的微电子科学与技术.文章重点综述了高迁移率锗与锗锡沟道金属氧化物半导体场效应晶体管(Metal Oxide Semiconductor Field Effect Transistor,MOSFET)以及隧穿场效应晶体管(Tunneling Field Effect Transistor,TFET)的研究进展.锗与锗锡具有比硅(Si)材料高的空穴和电子迁移率且容易实现硅衬底集成,是实现高迁移率沟道CMOS器件的理想备选材料.通过调节锡组分,锗锡材料可实现直接带隙结构,从而获得较高的带间隧穿几率,理论和实验证明可用锗锡实现高性能TFET器件.本文具体分析了锗锡MOSFETs和TFETs器件在材料生长、表面钝化、栅叠层、源漏工程、应变工程及器件可靠性等关键问题.
文摘This paper presents the impact of parameter fluctuation due to process variation on radio frequency （RF） stability performance of double gate tunnel FET （DG TFET）. The influence of parameter fluctuation due to process variation leads to DG TFET performance degradation. The RF figures of merit （FoM） such as cut-off frequency （ft）, maximum oscillation frequency （fmax） along with stability factor for different silicon body thickness, gate oxide thickness and gate contact alignment are obtained from extracted device parameters through numerical simulation. The impact of parameter fluctuation of silicon body thickness, gate oxide thickness and gate contact alignment was found significant and the result provides design guidelines ofDG TFET for RF applications.
基金Project supported by the Department of Science and Technology,Government of India under SERB Scheme(No.SERB/F/2660)
文摘In this paper,RF performance analysis of In As-based double gate（DG）tunnel field effect transistors（TFETs）is investigated in both qualitative and quantitative fashion.This investigation is carried out by varying the geometrical and doping parameters of TFETs to extract various RF parameters,unity gain cut-off frequency（f_t）,maximum oscillation frequency（f_（max））,intrinsic gain and admittance（Y）parameters.An asymmetric gate oxide is introduced in the gate-drain overlap and compared with that of DG TFETs.Higher ON-current（ION）of about 0.2 mA and less leakage current（IOFF）of 29 f A is achieved for DG TFET with gate-drain overlap.Due to increase in transconductance（g_m）,higher ft and intrinsic gain is attained for DG TFET with gate-drain overlap.Higher f_（max） of 985 GHz is obtained for drain doping of 5×10^（17）cm^（-3） because of the reduced gate-drain capacitance（C_（gd））with DG TFET with gate-drain overlap.In terms of Y-parameters,gate oxide thickness variation offers better performance due to the reduced values of Cgd.A second order numerical polynomial model is generated for all the RF responses as a function of geometrical and doping parameters.The simulation results are compared with this numerical model where the predicted values match with the simulated values.
文摘A double-gate tunnel field-effect transistor （DG tunnel FET） has been designed and investigated for various channel materials such as silicon （Si）, gallium arsenide （GaAs）, alminium gallium arsenide （A1xGa1-xAs） and CNT using a nano ViDES Device and TCAD SILVACO ATLAS simulator. The proposed devices are com- pared on the basis of inverse subthreshold slope （SS）, ION/IoFF current ratio and leakage current. Using Si as the channel material limits the property to reduce leakage current with scaling of channel, whereas the A1xGa1-xAs based DG tunnel FET provides a better ION/IOFF current ratio （2.51 × 10^6） as compared to other devices keeping the leakage current within permissible limits. The performed silmulation of the CNT based channel in the double-gate tunnel field-effect transistor using the nano ViDES shows better performace for a sub-threshold slope of 29.4 mV/dec as the channel is scaled down. The proposed work shows the potential of the CNT channel based DG tunnel FET as a futuristic device for better switching and high retention time, which makes it suitable for memory based circuits.
