An Empirical Direct Tunneling Current Expression for Ultra-Thin Oxide nMOSFETs

An empirical expression for the direct tunneling (DT) current is obtained.This expression can be used to calculate the DT current for nMOSFETs with ultra thin oxide when the oxide thickness is considered as an adjustable parameter.The results have good agreement with the experimental data.And the oxide thickness obtained is less than the value acquired from the capacitance voltage( C V )method.

Direct Tunneling Effect in Metal-Semiconductor Contacts Simulated with Monte Carlo Method

Considering the tunneling effect and the Schottky effect,the metal semiconductor contact is simulated by using self consistent ensemble Monte Carlo method.Under different biases or at different barrier heights,the investigation into the tunneling current indicates that the tunneling effect is of great importance under reverse biases.The Schottky barrier diode current due to Schottky effect is in agreement with the theoretical one.The barrier lowering is found a profound effect on the current transport at the metal semiconductor interface.

Direct Tunneling Currents Through Gate Dielectrics in Deep Submicron MOSFETs

A direct tunneling model through gate dielectric s in CMOS devices in the frame of WKB approximation is reported.In the model,an im proved one-band effective mass approximation is used for the hole quantization, where valence band mixing is taken into account.By comparing to the experiments, the model is demonstrated to be applicable to both electron and hole tunneling c urrents in CMOS devices.The effect of the dispersion in oxide energy gap on the tunneling current is also studied.This model can be further extended to study th e direct tunneling current in future high-k materials.

Gate Current for MOSFETs with High k Dielectric Materials

The MOSFET gate currents of high k gate dielectrics due to direct tunneling are investigated by using a new direct tunneling current model developed.The model includes both the inversion layer quantization effect with finite barrier height and the polysilicon depletion effect.The impacts of dielectric constant and conduction band offset as well as the band gap on the gate current are discussed.The results indicate that the gate dielectric materials with higher dielectric constant,larger conduction band offset and the larger band gap are necessary to reduce the gate current.The calculated results can be used as a guide to select the appropriate high k gate dielectric materials for MOSFETs.

Gate leakage current of NMOSFET with ultra-thin gate oxide

As dimensions of the metal-oxide-semiconductor field-effect transistor (MOSFET) are scaling down and the thickness of gate oxide is decreased,the gate leakage becomes more and more prominent and has been one of the most important limiting factors to MOSFET and circuits lifetime.Based on reliability theory and experiments,the direct tunneling current in lightly-doped drain (LDD) NMOSFET with 1.4 nm gate oxide fabricated by 90 nm complementary metal oxide semiconductor (CMOS) process was studied in depth.High-precision semiconductor parameter analyzer was used to conduct the tests.Law of variation of the direct tunneling (DT) current with channel length,channel width,measuring voltage,drain bias and reverse substrate bias was revealed.The results show that the change of the DT current obeys index law;there is a linear relationship between gate current and channel dimension;drain bias and substrate bias can reduce the gate current.

P-channel Ge/Si Hetero-nanocrystal Based MOSFET Memory

The charge storage characteristics of P-channel Ge/Si hetero-nanocrystal based MOSFET memory has been investigated and a logical array has been constructed using this memory cell. In the case of the thickness of tunneling oxide Tox = 2 nm and the dimensions of Si- and Ge-nanocrystal Dsi = DGe = 5 nm, the retention time of this device can reach ten years(～1 × 108 s) while the programming and erasing time achieve the orders of microsecond and millisecond at the control gate voltage | Vg | = 3 V with respect to N-wells,respectively. Therefore, this novel device, as an excellent nonvolatile memory operating at room temperature,is desired to obtain application in future VLSI.

Generation of mid-infrared supercontinuum by designing circular photonic crystal fiber

A circular photonic crystal fiber(C-PCF)based on As2 Se3 is designed,which has three zero dispersion wavelengths and flat dispersion.Using this fiber,a wide mid-infrared supercontinuum(MIR-SC)can be generated by launching a femtosecond pulse in the first anomalous dispersion region.The simulation results show that the MIR-SC is formed by soliton self-frequency shift and direct soliton spectrum tunneling on the long wavelength side and self-phase modulation,soliton fission on the short wavelength side.Further,optical shocking and four-wave mixing(FWM)are not conducive to the long-wavelength extension of MIR-SC,while the number and intensity of fundamental solitons have a greater effect on the short-wavelength extension of MIR-SC.The generation of optical shocking waves,FWM waves and fundamental solitons can be obviously affected by changing the fiber length and input pulse parameters,so that the spectrum range and flatness can be adjusted with great freedom.Finally,under the conditions of 4000 W pulse peak power,30 fs pulse width,47 mm fiber length,and 0 initial chirp,a wide MIR-SC with a coverage range of 2.535μm-16.6μm is obtained.These numerical results are encouraging because they demonstrate that the spread of MIR-SC towards the red and blue ends can be manipulated by choosing the appropriate incident pulse and designing optimized fiber parameters,which contributes to applications in such diverse areas as spectroscopy,metrology and tomography.

Analytical modeling of the direct tunneling current through high-k gate stacks for long-channel cylindrical surrounding-gate MOSFETs

An analytical direct tunneling gate current model for cylindrical surrounding gate（CSG） MOSFETs with high-k gate stacks is developed. It is found that the direct tunneling gate current is a strong function of the gate＇s oxide thickness, but that it is less affected by the change in channel radius. It is also revealed that when the thickness of the equivalent oxide is constant, the thinner the first layer, the smaller the direct tunneling gate current.Moreover, it can be seen that the dielectric with a higher dielectric constant shows a lower tunneling current than expected. The accuracy of the analytical model is verified by the good agreement of its results with those obtained by the three-dimensional numerical device simulator ISE.

Direct tunneling gate current model for symmetric double gate junctionless transistor with SiO_2/high-k gate stacked dielectric

A junctionless transistor is emerging as a most promising device for the future technology in the decananometer regime. To explore and exploit the behavior completely, the understanding of gate tunneling current is of great importance. In this paper we have explored the gate tunneling current of a double gate junctionless transistor（DGJLT） for the first time through an analytical model, to meet the future requirement of expected high-k gate dielectric material that could replace SiO2. We therefore present the high-k gate stacked architecture of the DGJLT to minimize the gate tunneling current. This paper also demonstrates the impact of conduction band offset,workfunction difference and k-values on the tunneling current of the DGJLT.

Degradation of nMOS and pMOSFETs with Ultrathin Gate Oxide Under DT Stress

The degradation of device parameters and the degradation of the stress induced leakage current （SILC） of thin tunnel gate oxide under constant direct-tunneling voltage stress are studied using nMOS and pMOSFETs with 1. 4nm gate oxides. Experimental results show that there is a linear correlation between the degradation of the SILC and the degradation of Vth in MOSFETs during different direct-tunneling （DT） stresses. A model of tunneling assisted by interface traps and oxide trapped positive charges is developed to explain the origin of SILC during DT stress.

Degradation of ultra-thin gate oxide LDD NMOSFET under GIDL stress

The degradation of device under GIDL （gate-induced drain leakage current） stress has been studied using LDD NMOSFETs with 1.4 nm gate oxides. Experimental result shows that the degradation of device parameters depends more strongly on Vd than on Vg. The characteristics of the GIDL current are used to analyze the damage generated during the stress. It is clearly found that the change of GIDL current before and after stress can be divided into two stages. The trapping of holes in the oxide is dominant in the first stage, but that of electrons in the oxide is dominant in the second stage. It is due to the common effects of edge direct tunneling and band-to-band tunneling. SILC（stress induced leakage current）in the NMOSFET decreases with increasing stress time under GIDL stress. The degradation characteristic of SILC also shows saturating time dependence. SILC is strongly dependent on the measured gate voltage. The higher the measured gate voltage, the less serious the degradation of the gate current. A likely mechanism is presented to explain the origin of SILC during GIDL stress.