Demands for low-energy microcontrollers have been increasing in recent years. Since most microcontrollers achieve user programmability by integrating nonvolatile (NV) memories such as flash memories for storing their ...Demands for low-energy microcontrollers have been increasing in recent years. Since most microcontrollers achieve user programmability by integrating nonvolatile (NV) memories such as flash memories for storing their programs, the large power consumption required in accessing an NV memory has become a major problem. This problem becomes critical when the power supply voltage of NV microcontrollers is decreased. We can solve this problem by introducing an instruction cache, thus reducing the access frequency of the NV memory. Unlike general-purpose microprocessors, microcontrollers used for real-time applications in embedded systems must accurately calculate program execution time prior to its execution. Therefore, we introduce a “transparent” instruction cache, which does not change the existing NV microcontroller’s cycle-level execution time, for reducing power and energy consumption, but not for improving the processing speed. We have conducted detailed microar chitecture design based on the architecture of a major industrial microcontroller, and we evaluated power and energy consumption for several benchmark programs. Our evaluation shows that the proposed instruction cache can successfully reduce energy consumption in a fairly wide range of practical NV microcontroller configurations.展开更多
An increase in the cache capacity is usually accompanied by a decrease in access speed.To balance the capacity and performance of caches,this paper proposes an instruction cache(ICache)architecture based on divide-by-...An increase in the cache capacity is usually accompanied by a decrease in access speed.To balance the capacity and performance of caches,this paper proposes an instruction cache(ICache)architecture based on divide-by-2 memory banks(D2MB-ICache).The control circuit and memory banks of D2MB-ICache work at the central processing unit(CPU)frequency and the divide-by-2 CPU frequency,respectively,so that the capacity of D2MB-ICache can be expanded without lowering its frequency.For sequential access,D2MB-ICache can output the required instruction from memory banks per CPU cycle by dividing the memory banks with a partition mechanism and employing an inversed clock technique.For non-sequential access,D2MB-ICache will fetch certain jump instructions one or two more times,so that it can catch the jump of the request address in time and send the correct instruction to the pipeline.Experimental results show that,compared with conventional ICache,D2MB-ICaches with the same and double capacities show a maximum frequency increase by an average of 14.6%and 6.8%,and a performance improvement by an average of 10.3%and 3.8%,respectively.Moreover,energy efficiency of 64-kB D2MB-ICache is improved by 24.3%.展开更多
在多核结构中,获得并行应用线程的安全、精确的最坏情况执行时间(worst case execution time,WCET)的最大挑战之一在于共享资源的竞争冲突检测.在共享Cache的多核处理器中,线程在共享Cache中的指令可能被其他并行线程的指令替换,从而导...在多核结构中,获得并行应用线程的安全、精确的最坏情况执行时间(worst case execution time,WCET)的最大挑战之一在于共享资源的竞争冲突检测.在共享Cache的多核处理器中,线程在共享Cache中的指令可能被其他并行线程的指令替换,从而导致了线程间在共享Cache上的干扰,因此多核结构下线程WCET需要考虑并行线程间在共享Cache上的干扰.在现有的简单地址映射干扰分析基础上,考虑了指令取指执行时序因素对干扰的影响,提出了非干扰状态的充分不必要条件,根据指令的取指执行时序范畴判断线程在共享Cache上的干扰状态.通过排除非干扰状态,可以进一步精确多核结构中线程的WCET估值.理论分析证明了该方法的有效性.实验结果表明,与当前现有的考虑执行周期和基于逻辑访问先后顺序的方法相比,基于时序方法下的WCET估值分别可以提高12%和7%的精确度.展开更多
文摘Demands for low-energy microcontrollers have been increasing in recent years. Since most microcontrollers achieve user programmability by integrating nonvolatile (NV) memories such as flash memories for storing their programs, the large power consumption required in accessing an NV memory has become a major problem. This problem becomes critical when the power supply voltage of NV microcontrollers is decreased. We can solve this problem by introducing an instruction cache, thus reducing the access frequency of the NV memory. Unlike general-purpose microprocessors, microcontrollers used for real-time applications in embedded systems must accurately calculate program execution time prior to its execution. Therefore, we introduce a “transparent” instruction cache, which does not change the existing NV microcontroller’s cycle-level execution time, for reducing power and energy consumption, but not for improving the processing speed. We have conducted detailed microar chitecture design based on the architecture of a major industrial microcontroller, and we evaluated power and energy consumption for several benchmark programs. Our evaluation shows that the proposed instruction cache can successfully reduce energy consumption in a fairly wide range of practical NV microcontroller configurations.
基金the Postgraduate Research Innovation Program of Jiangsu Province under Grant No.KYCX20_1936the Fundamental Research Funds for the Central Universities under Grant No.JUSRP51510the Key Research and Development Program of Jiangsu under Grant No.BE2019003-2.
文摘An increase in the cache capacity is usually accompanied by a decrease in access speed.To balance the capacity and performance of caches,this paper proposes an instruction cache(ICache)architecture based on divide-by-2 memory banks(D2MB-ICache).The control circuit and memory banks of D2MB-ICache work at the central processing unit(CPU)frequency and the divide-by-2 CPU frequency,respectively,so that the capacity of D2MB-ICache can be expanded without lowering its frequency.For sequential access,D2MB-ICache can output the required instruction from memory banks per CPU cycle by dividing the memory banks with a partition mechanism and employing an inversed clock technique.For non-sequential access,D2MB-ICache will fetch certain jump instructions one or two more times,so that it can catch the jump of the request address in time and send the correct instruction to the pipeline.Experimental results show that,compared with conventional ICache,D2MB-ICaches with the same and double capacities show a maximum frequency increase by an average of 14.6%and 6.8%,and a performance improvement by an average of 10.3%and 3.8%,respectively.Moreover,energy efficiency of 64-kB D2MB-ICache is improved by 24.3%.
文摘在多核结构中,获得并行应用线程的安全、精确的最坏情况执行时间(worst case execution time,WCET)的最大挑战之一在于共享资源的竞争冲突检测.在共享Cache的多核处理器中,线程在共享Cache中的指令可能被其他并行线程的指令替换,从而导致了线程间在共享Cache上的干扰,因此多核结构下线程WCET需要考虑并行线程间在共享Cache上的干扰.在现有的简单地址映射干扰分析基础上,考虑了指令取指执行时序因素对干扰的影响,提出了非干扰状态的充分不必要条件,根据指令的取指执行时序范畴判断线程在共享Cache上的干扰状态.通过排除非干扰状态,可以进一步精确多核结构中线程的WCET估值.理论分析证明了该方法的有效性.实验结果表明,与当前现有的考虑执行周期和基于逻辑访问先后顺序的方法相比,基于时序方法下的WCET估值分别可以提高12%和7%的精确度.
