SPLIT-ADC BASED DIGITAL BACKGROUND CALIBRATION FOR TIME-INTERLEAVED ADC

A novel Time-Interleaved Analog-to-Digital Converter (TIADC) digital background calibration for the mismatches of offsets, gain errors, and timing skews based on split-ADC is proposed. Firstly, the split-ADC channels in present TIADC architecture are designed to convert input signal at two different channel sampling rates so that redundant channel to facilitate pair permutation is avoided. Secondly, a high-order compensation scheme for correction of timing skew error is employed for effective calibration to preserve high-resolution when input frequency is high. Numerical simulation performed by MATLAB for a 14-bit TIADC based on 7 split-ADC channels shows that Signal-to-Noise and Distortion Ratio (SNDR) and Spurious Free Dynamic Range (SFDR) of the TIADC achieve 86.2 dBc and 106 dBc respectively after calibration with normalized input frequency near Nyquist frequency.

A FAST FOREGROUND DIGITAL CALIBRATION TECHNIQUE FOR PIPELINED ADC

Digital calibration techniques are widely developed to cancel the non-idealities of the pipelined Analog-to-Digital Converters (ADCs). This letter presents a fast foreground digital calibration technique based on the analysis of error sources which influence the resolution of pipelined ADCs. This method estimates the gain error of the ADC prototype quickly and calibrates the ADC simultaneously in the operation time. Finally, a 10 bit, 100 Ms/s pipelined ADC is implemented and calibrated. The simulation results show that the digital calibration technique has its efficiency with fewer operation cycles.

A Digital Background Calibration Technique for Successive Approximation Register Analog-to-Digital Converter

A digital background calibration technique that corrects the capacitor mismatches error is proposed for successive approximation register analog-to-digital converter (SAR ADC). The technique is implemented in SAR ADC which is based on tri-level switching. The termination capacitor in the Digital-to-Analog Converter (DAC) is regarded as a reference capacitor and the digital weights of all other unit capacitors are corrected with respect to the reference capacitor. To make a comparison between the size of the unit capacitor and that of the reference capacitor, each input sample is quantized twice. The unit capacitor being calibrated is swapped with the reference capacitor during the second conversion. The difference between the two conversion results is used to correct the digital weight of the unit capacitor under calibration. The calibration technique with two reference capacitors is presented to reduce the number of parameters to be estimated. Behavior simulation is performed to verify the proposed calibration technique by using a 12-bit SAR ADC with 3% random capacitor mismatch. The simulation results show that the Signal-to-Noise and Distortion Ratio (SNDR) is improved from 57.2 dB to 72.2 dB and the Spurious Free Dynamic Range (SFDR) is improved from 60.0 dB to 85.4 dB.

An in situ Digital Background Calibration Algorithm for Multi-Channel R-βR Ladder DACs

The R-2R resistor ladder is one of the best topologies for implementing compact-sized digital-to-analog converter(DAC)arrays in implantable neuro-stimulators.However,it has a limited resolution and considerable inter-channel variation due to component mismatches.To avoid losing analog information,we present sub-radix-2 DAC implemented by the R-βR resistor ladder in this paper.The digital successive approximation register(DSAR)algorithm corrects the transfer function of DACs based on their actual bit weights.Furthermore,a low-cost in situ adaptive bit-weight calibration(ABC)algorithm drives the analog output error between two DACs to zero by adjusting their bit weights automatically.The simulation results show that the proposed algorithm can calibrate the non-linear transfer function of each DAC and the gain error among multiple channels in the background.

DIGITAL BACKGROUND CALIBRATION OF CAPACITOR MISMATCHES AND HARMONIC DISTORTION IN PIPELINED ADC

A correlation-based digital background calibration algorithm for pipelined Analog-to- Digital Converters (ADCs) is presented in this paper. The merit of the calibration algorithm is that the main errors information, which include the capacitor mismatches and residue amplifier distortion, are extracted integrally. A modified 1st pipelined stage is adopted to solve the signal overflow caused by the Pseudo-random Noise (PN) sequences. Behavioral simulation results verify the effectiveness of the algorithm. It improves the Signal-to-Noise-plus-Distortion Ratio (SNDR) and Spurious-Free-Dynamic-Range (SFDR) of the pipelined ADC from 41.8 dB to 78.3 dB and 55.6 dB to 98.6 dB, respectively, which is comparable to the prior arts.

Whether the digital economy will successfully encourage the integration of urban and rural development: A case study in China

The digital economy has become an important driver for stimulating economic growth.The digital economy has now widely penetrated the fields of economy and society,providing new opportunities for the develop‐ment of urban-rural integration.Based on panel data for 30 provinces in China from 2011 to 2020,this study constructed an index system for the integration of the digital economy and the development of urban-rural areas and conducted a systematic measurement analysis.Additionally,we used a two-step system of GMM estimation to analyze the impact of the digital economy on the development of urban-rural integra‐tion.The findings demonstrate the significant imbalance paradox of China’s digital economy development,which is shown in a gradient where the eastern region is higher than the center and the central region is higher than the west.Urban-rural integration levels in China fluctuate and display geographical variance,typically displaying high levels in the east and low levels in the west.Urban-rural integration is significantly encouraged by the digital economy,yet it varies in variability between different areas and dimensions.Addi‐tionally,rural human capital moderates the favorable effects of the digital economy on urban-rural integra‐tion.As a result,in order to achieve the integrated development of urban and rural areas,it is imperative to fully exploit the active role of the digital economy,better support the development of rural revitalization,bridge the“digital divide”between urban and rural development,and build a strong foundation for the for‐mation of a digital urban-rural integrated development pattern with urban and rural areas and common con‐struction and sharing.

On-orbit Geometric Calibration and Preliminary Accuracy Evaluation of GF-14 Satellite

GF-14 satellite is a new generation of sub-meter stereo surveying and mapping satellite in China,carrying dual-line array stereo mapping cameras to achieve 1∶10000 scale topographic mapping without Ground Control Points(GCPs).In fact,space-based high-precision mapping without GCPs is a challenging task that depends on the close cooperation of several payloads and links,of which on-orbit geometric calibration is one of the most critical links.In this paper,the on-orbit geometric calibration of the dual-line array cameras of GF-14 satellite was performed using the control points collected in the high-precision digital calibration field,and the calibration parameters of the dual-line array cameras were solved as a whole by alternate iterations of forward and backward intersection.On this basis,the location accuracy of the stereo images using the calibration parameters was preliminarily evaluated by using several test fields around the world.The evaluation result shows that the direct forward intersection accuracy of GF-14 satellite images without GCPs after on-orbit geometric calibration reaches 2.34 meters(RMS)in plane and 1.97 meters(RMS)in elevation.

Digitally calibrated broadband dual-comb gases absorption spectral measurements

From the perspective of error compensation in the sampling process, a digital calibration algorithm was studied for the processing of spectral data in dual-comb spectroscopy. In this algorithm, dynamic adaptation to phase fluctuations maintained constant measurement results of spectral line positions and intensities. A mode-resolved broadband absorption spectrum was obtained over the full-spectral range of the comb with a Hertz linewidth of radio frequency comb mode.The measured spectrum spanned over 10 THz, which covered the multiplexed absorption regions of mixed gases, such as CO2 and N2 O. The calibrated interferograms were also capable of direct coherent averaging in the time domain. The transmittance obtained deviated from the theoretical calculation by no more than 2% in the whole spectral span.

Design of digital calibration based on variable step size of sub-binary SAR ADC

Addressing the impact of capacitor mismatch on the conversion accuracy of successive approximation register analog-to-digital converter(SAR ADC),a 12-bit 1 MS/s sub-binary SAR ADC designed using variable step size digital calibration was proposed.The least mean square(LMS)calibration algorithm was employed with a ramp signal used as the calibration input.Weight errors,extracted under injected disturbances,underwent iterative training to optimize weight values.To address the trade-off between conversion accuracy and speed caused by a fixed step size,a novel variable step size algorithm tailored for SAR ADC calibration was proposed.The core circuit and layout of the SAR ADC were implemented using the Taiwan Semiconductor Manufacturing Company(TSMC)0.35μm complementary metal-oxide-semiconductor(CMOS)commercial process.Simulation of the SAR ADC calibration algorithm was conducted using Simulink,demonstrating quick convergence and meeting conversion accuracy requirements compared to fixed step size simulation.The results indicated that the convergence speed of the LMS digital calibration algorithm with variable step size was approximately eight times faster than that with a fixed step size,also yielding a lower mean square error(MSE).After calibration,the simulation results for the SAR ADC exhibited an effective number of bit(ENOB)of 11.79 bit and a signal-to-noise and distortion ratio(SNDR)of 72.72 dB,signifying a notable enhancement in the SAR ADC performance.

Hierarchy structure characteristics analysis for the China Loess watersheds based on gully node calibration

A land surface region can be decomposed into a series of watershed units with a hierarchical organizational structure. For loess landform, the watershed is a basic spatial–structural unit that can express natural landforms, surface morphology characteristics, spatial organization and developmental evolution. In this research we adopted the concept of node calibration in the watershed structure unit, selected six complete watersheds on China Loess Plateau as the research areas to study the quantitative characteristics of the hierarchical structure in terms of watershed geomorphology based on digital elevation model(DEM) data, and then built a watershed hierarchical structure model that relies on gully structure feature points. We calculated the quantitative indices, such as elevation, flow accumulation and hypsometric integral and found there are remarkably closer linear correlation between flow accumulation and elevation with increasing gully order, and the same variation tendency of hypsometric integral also presented. The results showed that the characteristics of spatial structure become more stable, and the intensity of spatial aggregation gradually enhances with increasing gully order. In summary, from the view of gully node calibration, the China Loess watershed structure shows more significantly complex, and the developmental situation variation of the loess landforms also exhibited a fairly stable status with gully order increasing. So, the loess watershed structure and its changes constructed the complex system of the loess landform, and it has the great significance for studying the spatial pattern and evolution law of the watershed geomorphology.

Forensic Readiness: Emerging Discipline for Creating Reliable and Secure Digital Evidence

Traditional approaches to digital forensics reconstruct events within digital systems that often are not built for the creation of evidence; however,there is an emerging discipline of forensic readiness that examines what it takes to build systems and devices that produce digital data records for which admissibility is a requirement. This paper reviews the motivation behind research in this area,a generic technical solution that uses hardware-based security to bind digital records to a particular state of a device and proposed applications of this solution in concrete,practical scenarios. Research history in this area,the notion of secure digital evidence and a technical solution are discussed. A solution to creating hardware-based security in devices producing digital evidence was proposed in 2012. Additionally,this paper revises the proposal and discusses three distinct scenarios where forensic readiness of devices and secure digital evidence are relevant. It shows,how the different requirements of the three scenarios can be realized using a hardware-based solution. The scenarios are:lawful interception of voice communication,automotive black box,precise farming. These three scenarios come from very distinctive application domains. Nevertheless,they share a common set of security requirements for processes to be documented and data records to be stored.

Study on intelligent digital welding machine with a self-learning function

A design idea was proposed that it was about intelligent digital welding machine with self-learning and self- regulation functions. The overall design scheme of software and hardware was provided. It was introduced that a parameter self-learning algorithm was based on large-step calibration and partial Newton interpolation. Furthermore, experimental verification was carried out with different welding technologies. The results show that weld bead is pegrect. Therefore, good welding quality and stability are obtained, and intelligent regulation is realized by parameters self-learning.

A Timing Skew Calibration Scheme in Time-Interleaved ADC

This paper proposes a digital background calibration scheme for timing skew in time-interleaved analog-to-digital converters (TIADCs). It detects the relevant timing error by subtracting the output difference with the sum of the first derivative of the digital output. The least-mean-square (LMS) loop is exploited to compensate the timing skew. Since the calibration scheme depends on the digital output, all timing skew sources can be calibrated and the main ADC is maintained. The proposed scheme is effective within the entire frequency range of 0 ? fs/2. Compared with traditional calibration schemes, the proposed approach is more feasible and consumes significantly lesser power and smaller area.

Calibration of Camera with Large Field-of-View Based on Flexible Planar Target

For high precision calibration of camera with large field-of-view,massive calibration points will be needed if traditional methods are selected,which makes the calibration complex and time-consuming.In order to solve this problem,a calibration method based on flexible planar target is proposed.In this method,distortion factor is firstly acquired by the invariance of cross ratio,and existing feature points are adjusted with the distortion factor.Then,a large number of points that will be used for the calibration are constructed with the adjusted feature points.Simultaneously,Tsai method is modified so as to reduce the complexity of calibration,which makes the process linear.The simulation and real experiments show that the method proposed in this paper is simple,linear,accurate and robust,and the precision of this method is close to that of Tsai method using abundant points.The method can satisfy the requirement of high precision calibration for camera with large field-of-view.

Implementation and integration of a systematic DBPM calibration with PLL frequency synthesis and FPGA

Beam current dependence resulted from nonlinearity and asymmetry of the four channels of digital BPM(Beam Position Monitor) processor deteriorates the BPM performance.A systematic solution based on signal source calibration tactics has been carried out to rectify this defect.It is optimized for implementation in FPGA.Mathematical illustrations of the calibration method,hardware and software design and implementation are presented.A signal source circuit using frequency synthesis technique is designed as calibration standard.Data acquisition system using JAVA web technology and Ethernet is introduced.Integrated FPGA implementation code architecture is presented,and experimental test results show that the method implemented in FPGA is feasible.Compared to other methods,our approach can rectify the nonlinearity and asymmetry simultaneously.The whole solution is integrated into the DBPM processor and can be executed online.

Geometric calibration of high-resolution remote sensing sensors

This paper introduces the applications of high-resolution remote sensing imagery and the necessity of geometric calibration for remote sensing sensors considering assurance of the geometric accuracy of remote sensing imagery. Then the paper analyzes the general methodology of geometric calibration. Taking the DMC sensor geometric calibration as an example, the paper discusses the whole calibration procedure. Finally, it gave some concluding remarks on geometric calibration of high-resolution remote sensing sensors.

Clustering compression-based computation-efficient calibration method for digital twin modeling of HVAC system

Digital twin is regarded as the next-generation technology for the effective operation of heating,ventilation and air conditioning(HVAC)systems.It is essential to calibrate the digital twin models to match them closely with real physical systems.Conventional real-time calibration methods cannot satisfy such requirements since the computation loads are beyond acceptable tolerances.To address this challenge,this study proposes a clustering compression-based method to enhance the computation efficiency of digital twin model calibration for HVAC systems.This method utilizes clustering algorithms to remove redundant data for achieving data compression.Moreover,a hierarchical multi-stage heuristic model calibration strategy is developed to accelerate the calibration of similar component models.Its basic idea is that once a component model is calibrated by heuristic methods,its optimal solution is utilized to narrow the ranges of parameter probability distributions of similar components.By doing so,the calibration process can be guided,so that fewer iterations would be used.The performance of the proposed method is evaluated using the operational data from an HVAC system in an industrial building.Results show that the proposed clustering compression-based method can reduce computation loads by 97%,compared to the conventional calibration method.And the proposed hierarchical heuristic model calibration strategy is capable of accelerating the calibration process after clustering and saves 14.6%of the time costs.

Positioning of Screw Holes Group Based on Digital Camera and Digital Control Drilling

Positioning of screw holes is an important production procedure for steel construction connecting with bolts. In this paper, a new production method is presented, in which the digital camera is used for taking pictures of screw holes and other techniques are advanced. This paper also indicates that the pixels of CCD chip in photogrammetry should be chosen as all geometric units in an image, such as interior elements and all kinds of distortions. The measure can also simplify the camera calibration for determining the size of non-square pixel.

A 1-GHz, 7-mW, 8-Bit Subranging ADC without Resistor Ladder Using Built-In Threshold Calibration

A subranging analog-to-digital converter (ADC) features high-speed and relatively low-power. The limiting factors of power reduction in subranging ADCs are the resistor ladder and the comparator. We propose an ADC architecture combining a capacitive digital-to-analog convertor and built-in threshold calibration to eliminate the resistor ladder, resulting in a low-power subranging ADC. We also propose a calibration technique comprising of metal-oxide-metal capacitor, MOS switch, and scaling capacitor to reduce the power consumption of the comparator and an offset drift compensation technique to enable precise foreground calibration. We designed an 8-bit, 1-GHz subranging ADC by applying these techniques, and post-layout simulation results demonstrated a power consumption of 7 mW and figure of merit of 51 fJ/conv.-step.