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Ultra-low-voltage-trigger thyristor for on-chip ESD protection without extra process cost 被引量:1
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作者 单毅 何军 黄文毅 《Journal of Semiconductors》 EI CAS CSCD 北大核心 2009年第7期80-82,共3页
A new thyristor is proposed and realized in the foundry's 0.18-μm CMOS process for electrostatic dis-charge(ESD) protection.Without extra mask layers or process steps, the new ultra-low-voltage-trigger thyristor(... A new thyristor is proposed and realized in the foundry's 0.18-μm CMOS process for electrostatic dis-charge(ESD) protection.Without extra mask layers or process steps, the new ultra-low-voltage-trigger thyristor(ULVT thyristor) has a trigger voltage as low as 6.7 V and an ESD robustness exceeding 50 mA/μm, which enables effective ESD protection.Compared with the traditional medium-voltage-trigger thyristor(MVT thyristor), the new structure not only has a lower trigger voltage, but can also provide better ESD protection under both positive and negative ESD zapping conditions. 展开更多
关键词 THYRISTOR electro-static discharge ultra-low-voltage-trigger positive negative
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