Regulation of interlayer channels of graphene oxide nanosheets in ultra-thin Pebax mixed-matrix membranes for CO_(2) capture

For the application of carbon capture by membrane process,it is crucial to develop a highly permeable CO_(2)-selective membrane.In this work,we reported an ultra-thin polyether-block-amide(Pebax)mixedmatrix membranes(MMMs)incorporated by graphene oxide(GO),in which the interlayer channels were regulated to optimize the CO_(2)/N_(2) separation performance.Various membrane preparation conditions were systematically investigated on the influence of the membrane structure and separation performance,including the lateral size of GO nanosheets,GO loading,thermal reduction temperature,and time.The results demonstrated that the precisely regulated interlayer channel of GO nanosheets can rapidly provide CO_(2)-selective transport channels due to the synergetic effects of size sieving and preferential adsorption.The GO/Pebax ultra-thin MMMs exhibited CO_(2)/N_(2) selectivity of 72 and CO_(2) permeance of 400 GPU(1 GPU=106 cm^(3)(STP)·cm^(2)·s^(-1)·cmHg^(-1)),providing a promising candidate for CO_(2) capture.

Substrate Hot Holes Injection Induced Breakdown Characteristics of Thin Gate Oxides

A substrate hot holes injection method is used to quantitatively examine the roles of electrons and holes separately in thin gate oxides breakdown.The shift of threshold voltage under different stress is discussed.It is indicated that positive charges are trapped in SiO 2 while hot electrons are necessary for SiO 2 breakdown.The anode holes injection model and the electron traps generation model is linked into a consistent model,describing the oxide wearout as an electron correlated holes trap creation process.The results show that the limiting factor in thin gate oxides breakdown depends on the balance between the amount of injected hot electrons and holes.The gate oxides breakdown is a two step process.The first step is hot electron's breaking Si-O bonds and producing some dangling bonds to be holes traps.Then the holes are trapped and a conducted path is produced in the oxides.The joint effect of hot electrons and holes makes the thin gate oxides breakdown complete.

Effect of Metal Contamination on Characteristics of Ultra-Thin Gate Oxide

The purpose of this work relates to study on the characteristics of ultra thin gate oxide (2 5nm thickness) and the effect of metal Al,Zr,and Ta contamination on GOI.The controlled metallic contamination experiments are carried out by depositing a few ppm contaminated metal and low pH solutions on the wafers.The maximum metal surface concentration is controlled at about 10 12 cm -2 level in order to simulate metal contamination during ultra clean processing.A ramped current stress for intrinsic charge to breakdown measurements with gate injection mode is used to examine the characteristics of these ultra thin gate oxides and the effect of metal contamination on GOI.It is the first time to investigate the influence of metal Zr and Ta contamination on 2 5nm ultra thin gate oxide.It is demonstrated that there is little effect of Al contamination on GOI,while Zr contamination is the most detrimental to GOI,and early breakdown has happened to wafers contaminated by Ta.

The conduction mechanism of stress induced leakage current through ultra-thin gate oxide under constant voltage stresses

The conduction mechanism of stress induced leakage current （SILC） through 2nm gate oxide is studied over a gate voltage range between 1.7V and stress voltage under constant voltage stress （CVS）. The simulation results show that the SILC is formed by trap-assisted tunnelling （TAT） process which is dominated by oxide traps induced by high field stresses. Their energy levels obtained by this work are approximately 1.9eV from the oxide conduction band, and the traps are believed to be the oxygen-related donor-like defects induced by high field stresses. The dependence of the trap density on stress time and oxide electric field is also investigated.

Scaling effects of single-event gate rupture in thin oxides

The dynamics of the excess carriers generated by incident heavy ions are considered in both SiO2 and Si substrate. Influences of the initial radius of the charge track, surface potential decrease, external electric field, and the LET value of the incident ion on internal electric field buildup are analyzed separately. Considering the mechanisms of recombination, impact ionization, and bandgap tunneling, models are verified by using published experimental data. Moreover, the scaling effects of single-event gate rupture in thin gate oxides are studied, with the feature size of the MOS device down to 90 nm. The walue of the total electric field decreases rapidly along with the decrease of oxide thickness in the first period （1 2 nm to 3.3 nm）, and then increases a little when the gate oxide becomes thinner and thinner （3.3 nm to 1.8 nm）.

Gate leakage current of NMOSFET with ultra-thin gate oxide

As dimensions of the metal-oxide-semiconductor field-effect transistor (MOSFET) are scaling down and the thickness of gate oxide is decreased,the gate leakage becomes more and more prominent and has been one of the most important limiting factors to MOSFET and circuits lifetime.Based on reliability theory and experiments,the direct tunneling current in lightly-doped drain (LDD) NMOSFET with 1.4 nm gate oxide fabricated by 90 nm complementary metal oxide semiconductor (CMOS) process was studied in depth.High-precision semiconductor parameter analyzer was used to conduct the tests.Law of variation of the direct tunneling (DT) current with channel length,channel width,measuring voltage,drain bias and reverse substrate bias was revealed.The results show that the change of the DT current obeys index law;there is a linear relationship between gate current and channel dimension;drain bias and substrate bias can reduce the gate current.

Breakdown Voltage and Charge to Breakdown Investigation of Gate Oxide of 0.18μm Dual Gate CMOS Process with Different Measurement Methods

Breakdown voltage （Vbd） and charge to breakdown （Qbd） are two parameters often used to evaluate gate oxide reliability. In this paper,we investigate the effects of measurement methods on Vbd and Qbd of the gate oxide of a 0.18μm dual gate CMOS process. Voltage ramps （V-ramp） and current ramps （J-ramp） are used to evaluate gate oxide reliability. The thin and thick gate oxides are all evaluated in the accumulation condition. Our experimental results show that the measurement methods affect Vbd only slightly but affect Qbd seriously,as do the measurement conditions.This affects the I-t curves obtained with the J-ramp and V-ramp methods. From the I-t curve,it can be seen that Qbd obtained using a J-ramp is much bigger than that with a V-ramp. At the same time, the Weibull slopes of Qbd are definitely smaller than those of Vbd. This means that Vbd is more reliable than Qbd, Thus we should be careful to use Qbd to evaluate the reliability of 0.18μm or beyond CMOS process gate oxide.

Analysis of hot-carrier degradation in N-LDMOS transistor with step gate oxide

In order to minimize the hot-carrier effect（HCE）and maintain on-state performance in the high voltage N-type lateral double diffused MOS（N-LDMOS）, an optimized device structure with step gate oxide is proposed. Compared with the conventional configuration, the electric field under the gate along the Si-SiO2 interface in the presented N-LDMOS can be greatly reduced, which favors reducing the hot-carrier degradation. The step gate oxide can be achieved by double gate oxide growth, which is commonly used in some smart power ICs. The differences in hot-carrier degradations between the novel structure and the conventional structure are investigated and analyzed by 2D technology computer-aided design（TCAD）numerical simulations, and the optimal length of the thick gate oxide part in the novel N-LDMOS device can also be acquired on the basis of maintaining the characteristic parameters of the conventional device. Finally, the practical degradation measurements of some characteristic parameters can also be carried out. It is found that the hot-carrier degradation of the novel N-LDMOS device can be improved greatly.

SILC Mechanism in Degraded Gate Oxide of Different Thickness

It is shown that traps are generated asymmetrically in the thin gate oxides with different thickness during high field degradation,as well as the multi-mechanism plays role in the Stress Induced Leakage Current (SILC).These factors perform differently in gate oxide of different thickness.A comparison is drew between several analyzing models.Trap assisted tunneling is preferred for thinner samples,while Pool-Frankel like mechanism or thermal emission mechanism should apply to the thick ones.

New Forward Gated-Diode Technique for Separating Front Gate Interface- from Oxide-Traps Induced by Hot-Carrier-Stress in SOI-NMOSFETs

The front gate interface and oxide traps induced by hot carrier stress in SOI NMOSFETs are studied.Based on a new forward gated diode technique,the R G current originating from the front interface traps is measured,and then the densities of the interface and oxide traps are separated independently.The experimental results show that the hot carrier stress of front channel not only results in the strong generation of the front interface traps,but also in the significant oxide traps.These two kinds of traps have similar characteristic in increasing with the hot carrier stress time.This analysis allows one to obtain a clear physical picture of the effects of the hot carrier stress on the generating of interface and oxide traps,which help to understand the degradation and reliability of the SOI MOSFETs.

High performance trench MOS barrier Schottky diode with high-k gate oxide

A novel trench MOS barrier Schottky diode（TMBS） device with a high-k material introduced into the gate insulator is reported, which is named high-k TMBS. By simulation with Medici, it is found that the high-k TMBS can have 19.8% lower leakage current while maintaining the same breakdown voltage and forward turn-on voltage compared with the conventional regular trench TMBS.

Dual-gate lateral double-diffused metal—oxide semiconductor with ultra-low specific on-resistance

A new high voltage trench lateral double-diffused metal–oxide semiconductor （LDMOS） with ultra-low specific onresistance （R on,sp ） is proposed. The structure features a dual gate （DG LDMOS）： a planar gate and a trench gate inset in the oxide trench. Firstly, the dual gate can provide a dual conduction channel and reduce R on,sp dramatically. Secondly, the oxide trench in the drift region modulates the electric field distribution and reduces the cell pitch but still can maintain comparable breakdown voltage （BV）. Simulation results show that the cell pitch of the DG LDMOS can be reduced by 50% in comparison with that of conventional LDMOS at the equivalent BV; furthermore, R on,sp of the DG LDMOS can be reduced by 67% due to the smaller cell pitch and the dual gate.

Novel Oxide Trap Behavior in Ultra Thin Gate and Its Study by PDO Method

The degradation of MOSFETs under high field stress has been investigated for a l ong time. The degradation is due to the newly generated traps. As the gate thick ness scaled down rapidly, a conventional method for detecting oxide traps, such as C-V or subthreshold swing, is no longer effective. Some new phenome na a lso appear, such as Stress Induced Leakage Current (SILC) and soft-breakdown. T he oxide traps’ behavior and their characteristics are the key problems in the s tudy of degradation. By extracting the change of transition coefficients from th e I-V curve and using the PDO (Proportional Differential Operator) meth od, various oxide traps can be distinguished and as would be helpful in the dete rmination of trap behavior changes during the degradation process.

Investigation of gate oxide traps effect on NAND flash memory by TCAD simulation

The effects of gate oxide traps on gate leakage current and device performance of metal–oxide–nitride–oxide–silicon(MONOS)-structured NAND flash memory are investigated through Sentaurus TCAD. The trap-assisted tunneling(TAT)model is implemented to simulate the leakage current of MONOS-structured memory cell. In this study, trap position, trap density, and trap energy are systematically analyzed for ascertaining their influences on gate leakage current, program/erase speed, and data retention properties. The results show that the traps in blocking layer significantly enhance the gate leakage current and also facilitates the cell program/erase. Trap density ~10^(18) cm^(-3) and trap energy ~ 1 eV in blocking layer can considerably improve cell program/erase speed without deteriorating data retention. The result conduces to understanding the role of gate oxide traps in cell degradation of MONOS-structured NAND flash memory.

Low voltage substrate current： a monitor for interface states generation in ultra-thin oxide n-MOSFETs under constant voltage stresses

The low voltage substrate current （Ib） has been studied based on generation kinetics and used as a monitor of interface states （Nit） generation for ultra-thin oxide n-MOSFETs under constant voltage stress. It is found that the low voltage Ib is formed by electrons tunnelling through interface states, and the variations of Ib（△Ib） are proportional to variations of Nit （△Nit）. The Nit energy distributions were determined by differentiating Nit（Vg）. The results have been compared with that measured by using gate diode technique.

Investigation on the passivation,band alignment,gate charge,and mobility degradation of the Ge MOSFET with a GeO/Al;O;gate stack by ozone oxidation

Ge has been an alternative channel material for the performance enhancement of complementary metal-oxide-semiconductor(CMOS)technology applications because of its high carrier mobility and superior compatibility with Si CMOS technology.The gate structure plays a key role on the electrical property.In this paper,the property of Ge MOSFET with Al_(2)O_(3)/GeO_(x)/Ge stack by ozone oxidation is reviewed.The GeO_(x)passivation mechanism by ozone oxidation and band align-ment of Al2O3/GeO_(x)/Ge stack is described.In addition,the charge distribution in the gate stack and remote Coulomb scatter-ing on carrier mobility is also presented.The surface passivation is mainly attributed to the high oxidation state of Ge.The en-ergy band alignment is well explained by the gap state theory.The charge distribution is quantitatively characterized and it is found that the gate charges make a great degradation on carrier mobility.These investigations help to provide an impressive un-derstanding and a possible instructive method to improve the performance of Ge devices.

Impact of STI indium implantation on reliability of gate oxide

The impacts of shallow trench isolation(STI)indium implantation on gate oxide and device characteristics are studied in this work.The stress modulation effect is confirmed in this research work.An enhanced gate oxide oxidation rate is observed due to the enhanced tensile stress,and the thickness gap is around 5%.Wafers with and without STI indium implantation are manufactured using the 150-nm silicon on insulator(SOI)process.The ramped voltage stress and time to breakdown capability of the gate oxide are researched.No early failure is observed for both wafers the first time the voltage is ramped up.However,a time dependent dielectric breakdown(TDDB)test shows more obvious evidence that the gate oxide quality is weakened by the STI indium implantation.Meanwhile,the device characteristics are compared,and the difference between two devices is consistent with the equivalent oxide thickness(EOT)gap.

Low-Frequency Noise in Amorphous Indium Zinc Oxide Thin Film Transistors with Aluminum Oxide Gate Insulator

Low-frequency noise（LFN） in all operation regions of amorphous indium zinc oxide（a-IZO） thin film transistors（TFTs） with an aluminum oxide gate insulator is investigated. Based on the LFN measured results, we extract the distribution of localized states in the band gap and the spatial distribution of border traps in the gate dielectric,and study the dependence of measured noise on the characteristic temperature of localized states for a-IZO TFTs with Al2 O3 gate dielectric. Further study on the LFN measured results shows that the gate voltage dependent noise data closely obey the mobility fluctuation model, and the average Hooge＇s parameter is about 1.18×10^-3.Considering the relationship between the free carrier number and the field effect mobility, we simulate the LFN using the △N-△μ model, and the total trap density near the IZO/oxide interface is about 1.23×10^18 cm^-3eV^-1.

Low switching loss and increased short-circuit capability split-gate SiC trench MOSFET with p-type pillar

A split-gate SiC trench gate MOSFET with stepped thick oxide, source-connected split-gate(SG), and p-type pillar(ppillar) surrounded thick oxide shielding region(GSDP-TMOS) is investigated by Silvaco TCAD simulations. The sourceconnected SG region and p-pillar shielding region are introduced to form an effective two-level shielding, which reduces the specific gate–drain charge(Q_(gd,sp)) and the saturation current, thus reducing the switching loss and increasing the short-circuit capability. The thick oxide that surrounds a p-pillar shielding region efficiently protects gate oxide from being damaged by peaked electric field, thereby increasing the breakdown voltage(BV). Additionally, because of the high concentration in the n-type drift region, the electrons diffuse rapidly and the specific on-resistance(Ron,sp) becomes smaller.In the end, comparing with the bottom p~+ shielded trench MOSFET(GP-TMOS), the Baliga figure of merit(BFOM,BV~2/R_(on,sp)) is increased by 169.6%, and the high-frequency figure of merit(HF-FOM, R_(on,sp) × Q_(gd,sp)) is improved by310%, respectively.

Amorphous gallium oxide homojunction-based optoelectronic synapse for multi-functional signal processing

In the era of accelerated development in artificial intelligence as well as explosive growth of information and data throughput,underlying hardware devices that can integrate perception and memory while simultaneously offering the bene-fits of low power consumption and high transmission rates are particularly valuable.Neuromorphic devices inspired by the human brain are considered to be one of the most promising successors to the efficient in-sensory process.In this paper,a homojunction-based multi-functional optoelectronic synapse(MFOS)is proposed and testified.It enables a series of basic electri-cal synaptic plasticity,including paired-pulse facilitation/depression(PPF/PPD)and long-term promotion/depression(LTP/LTD).In addition,the synaptic behaviors induced by electrical signals could be instead achieved through optical signals,where its sen-sitivity to optical frequency allows the MFOS to simulate high-pass filtering applications in situ and the perception capability integrated into memory endows it with the information acquisition and processing functions as a visual system.Meanwhile,the MFOS exhibits its performances of associative learning and logic gates following the illumination with two different wave-lengths.As a result,the proposed MFOS offers a solution for the realization of intelligent visual system and bionic electronic eye,and will provide more diverse application scenarios for future neuromorphic computing.