An Improved Angle Polishing Method for Measuring Subsurface Damage in Silicon Wafers

We present an improved angle polishing method in which the end of the cover slice near the glue layer is beveled into a thin,defect-free wedge,the straight edge of which is used as the datum for measuring the depth of subsurface damage. The bevel angle can be calculated from the interference fringes formed in the wedge. The minimum depth of the subsurface damage that can be measured by this method is a few hundred nanometers. Our results show that the method is straightforward, accurate, and convenient.

A Diamond Electrochemical Cleaning Technique for Organic Contaminants on Silicon Wafer Surfaces

Peroxodiphosphate anion （a powerful oxidant） can be formed in a special water-based cleaning agent through an electrochemical reaction on boron-doped diamond electrodes. This electrochemical reaction was applied during the oxidation,decomposition, and removal of organic contaminations on a silicon wafer surface, and it was used as the first step in the diamond electrochemical cleaning technique （DECT）. The cleaning effects of DECT were compared with the RCA cleaning technique, including the silicon surface chemical composition that was observed with X-ray photoelectron spectroscopy and the morphology observed with atomic force microscopy. The measurement results show that the silicon surface cleaned by DECT has slightly less organic residue and lower micro-roughness,so the new technique is more effective than the RCA cleaning technique.

Transfer of Thin Epitaxial Silicon Films by Wafer Bonding and Splitting of Double Layered Porous Silicon for SOI Fabrication

A double layered porous silicon with different porosity is formed on a heavy doped p type Si(111) substrate by changing current density during the anodizing.Then a high quality epitaxial mono crystalline silicon film is grown on the porous silicon using an ultra high vacuum electron beam evaporator.This wafer is bonded with other silicon wafer with a thermal oxide layer at room temperature.The bonded pairs are split along the porous silicon layer during subsequent thermal annealing.Thus the epitaxial Si film is transferred to the oxidized wafer to form a silicon on insulator structure.SEM,XTEM,spreading resistance probe and Hall measurement show that the SOI structure has good structural and electrical quality.

Effect of Rapid Thermal Annealing Ambient on Gettering Efficiency and Surface Microstructure in 300mm CZ Silicon Wafers

The effect of rapid thermal annealing （RTA） ambient on denuded zone and oxygen precipitates in Czochralski （CZ） silicon wafers is studied in this paper. N2 and a N2/NH3 mixture are used as RTA ambient. It is demonstrated that a high density of oxygen precipitates and thin denuded zone are obtained in N2/NH3 ambient,while a relatively lower density of oxygen precipitates and thicker denuded zone are observed in N2 ambient. As the RTA duration times increased, the oxygen precipitate density increased and the denuded zone depth decreased. X-ray photoelectron spectroscopy （XPS） data and atomic force microscope （AFM） results show that there RTA process,which can explain the different effect of RTA was a surface nitriding reaction during the N2/NH3 ambient ambient.

STUDIES OF SURFACE GRINDING TEMPERATURE AFFECTED BY DIFFERENT GRINDING WAYS OF SILICON WAFER

The surface grinding temperature of the silicon wafer ground by diamond wheels is studied.Rudimentally,the properties of the surface grinding temperature generated by two grinding methods,ground by straight and cup wheels respectively,are analyzed.In addition,considering the effects of grain size and grinding depth on surface grinding temperature during these two grinding processes,significant results and conclusions are obtained from experimental research.

Microstructure studies of the grinding damage in monocrystalline silicon wafers

The depth and nature of the subsurface damage in a silicon wafer will limit the performance of IC components. Damage microstructures of the silicon wafers ground by the #325, #600, and #2000 grinding wheels was analyzed. The results show that many microcracks, fractures, and dislocation rosettes appear in the surface and subsurface of the wafer ground by the #325 grinding wheel. No obvious microstructure change exists. The amorphous layer with a thickness of about 100 nm, microcracks, high density dislocations, and polycrystalline silicon are observed in the subsurface of the wafer ground by the #600 grinding wheel. For the wafer ground by the #2000 grinding wheel, an amorphous layer of about 30 nm thickness, a polycrystalline silicon layer, a few dislocations, and an elastic deformation layer exist. In general, with the decrease in grit size, the material removal mode changes from micro-fracture mode to ductile mode gradually.

Formation of subsurface cracks in silicon wafers by grinding

Single-crystal silicon is an important material in the semiconductor and optical industries.However,being hard and brittle,a silicon wafer is vulnerable to subsurface cracks(SSCs)during grinding,which is detrimental to the performance and lifetime of a wafer product.Therefore,studying the formation of SSCs is important for optimizing SSC-removal processes and thus improving surface integrity.In this study,a statistical method is used to study the formation of SSCs induced during grinding of silicon wafers.The statistical results show that grinding-induced SSCs are not stochastic but anisotropic in their distributions.Generally,when grinding with coarse abrasive grains,SSCs form along the cleavage planes,primarily the{111}planes.However,when grinding with finer abrasive grains,SSCs tend to form along planes with a fracture-surface energy higher than that of the cleavage planes.These findings provide a guidance for the accurate detection of SSCs in ground silicon wafers.

Residual stress analysis on silicon wafer surface layers induced by ultraprecision grinding

Grinding residual stresses of silicon wafers affect the performance of IC circuits. Based on the wafer rotation ultra-precision grinding ma-chine, the residual stress distribution along grinding marks and ground surface layer depth of the ground wafers are investigated using Raman microspectroscopy. The results show that the ground wafer surfaces mainly present compressive stress. The vicinity of pile-ups between two grinding marks presents higher a compressive stress. The stress value of the rough ground wafer is the least because the material is removed by the brittle fracture mode. The stress of the semi-fine ground wafer is the largest because the wafer surface presents stronger phase trans-formations and elastic-plastic deformation. The stress of the fine ground wafer is between the above two. The strained layer depths for the rough, semi-fine, and fine ground wafers are about 7.6 m, 2.6 m, and 1.1 m, respectively. The main reasons for generation of residual stresses are phase transformations and elastic-plastic deformation.

Challenges in Processing Diamond Wire Cut and Black Silicon Wafers in Large-Scale Manufacturing of High Efficiency Solar Cells

Texturing of diamond wire cut wafers using a standard wafer etch process chemistry has always been a challenge in solar cell manufacturing industry. This is due to the change in surface morphology of diamond wire cut wafers and the abundant presence of amorphous silicon content, which are introduced from wafer manufacturing industry during sawing of multi-crystalline wafers using ultra-thin diamond wires. The industry standard texturing process for multi-crystalline wafers cannot deliver a homogeneous etched silicon surface, thereby requiring an additive compound, which acts like a surfactant in the acidic etch bath to enhance the texturing quality on diamond wire cut wafers. Black silicon wafers on the other hand require completely a different process chemistry and are normally textured using a metal catalyst assisted etching technique or by plasma reactive ion etching technique. In this paper, various challenges associated with cell processing steps using diamond wire cut and black silicon wafers along with cell electrical results using each of these wafer types are discussed.

Large energy-loss straggling of swift heavy ions in ultra-thin active silicon layers

Monte Carlo simulations reveal considerable straggling of energy loss by the same ions with the same energy in fully-depleted silicon-on-insulator （FDSOI） devices with ultra-thin sensitive silicon layers down to 2.5 rim. The absolute straggling of deposited energy decreases with decreasing thickness of the active silicon layer. While the relative straggling increases gradually with decreasing thickness of silicon films and exhibits a sharp rise as the thickness of the silicon film descends below a threshold value of 50 nm, with the dispersion of deposited energy ascending above ~10%. Ion species and energy dependence of the energy-loss straggling are also investigated. For a given beam, the dispersion of deposited energy results in large uncertainty on the actual linear energy transfer （LET） of incident ions, and thus single event effect （SEE） responses, which pose great challenges for traditional error rate prediction methods.

Electrochemical behaviors of silicon wafers in silica slurry

The electrochemical behaviors of n-type silicon wafers pH value and solid content of the slurry on the corrosion of silicon in silica-based slurry were investigated, and the influences of the wafers were studied by using electrochemical DC polarization and AC impedance techniques. The results revealed that these factors affected the corrosion behaviors of silicon wafers to different degrees and had their suitable parameters that made the maximum corrosion rate of the wafers. The corrosion potential of （100） sttrface was lower than that of（111）, whereas the current density of （100） was much higher than that of（111）.

DESIGN AND FABRICATION OF SUPER-HYDROPHOBIC SURFACES ON SILICON WAFERS AND STUDY OF EFFECTS TO HYDROPHOBICITY

Some superhydrophobic siliconbased surfaces with periodic square pillar array microstructures were designed and fabricated, also their apparent contact angles （CAs） were quantitatively measured. On the basis of the classical Wenzel＇s theory and Cassie＇s theory, two generally applicable equations corresponding of the cases of wetted contact and composite contact, which could reflect the relations between geometrical parameters of square pillar microstructures and apparent CAs, were educed. Then a theoretical prediction of the fabricated siliconbased surfaces was carried out by the equations, which was compatible with the result of experimental measurement, and this showed the rationality of the educed equations. The CAs of the surface prepared by merely plasma etching to create microstructures and by only Teflon treating were compared, and the result indicated that the effect of the former on achieving hydrophobic surfaces was greater than that of the later. Under the premise of synthetically considering transition between the two contact states, the effects of geometrical parameters of the square pillar microstructures to hydrophobicity were analyzcation, thereon a design condition and a design principle for super-hydrophobic surfaces which would be of specific application value were summarized.

Development of a miniature silicon wafer fuel cell using L-ascorbic acid as fuel

In the current studies a miniature silicon wafer fuel cell(FC) using L-ascorbic acid as fuel was developed. The cell employs L-ascorbic acid and air as reactants and a thin polymer electrolyte as a separator. Inductively coupled plasma(ICP) silicon etching was employed to fabricate high aspect-ratio columns on the silicon substrate to increase the surface area. A thin platinum layer deposited directly on the silicon surface by the sputtering was used as the catalyst layer for L-ascorbic acid electro-oxidation. Cyclic voltammetry shows that the oxidation of L-ascorbic acid on the sputtered platinum layer is irreversible and that the onset potentials for the oxidation of L-ascorbic acid are from 0.27 V to 0.35 V versus an Ag/AgCl reference electrode. It is found that at the room temperature,with 1 mol/L L-ascorbic acid/PBS(phosphate buffered solution) solution pumped to the anode at 1 ml/min flow rate and air spontaneously diffusing to the cathode as the oxidant,the maximum output power density of the cell was 1.95 mW/cm2 at a current density of 10 mA/cm2.

New process for production of ultra-thin grain oriented silicon steel

The Hi-B silicon steels were cold rolled by cross shear rolling (CSR) with different mismatch speed ratio(MSR)s and conventional rolling(CR) respectively, followed by primary recrystallization annealing. The effects of MSR and annealing temperature on magnetic properties of ultra-thin grain oriented silicon steel were analyzed. Experimental results show that, with the increase of MSR, the magnetic properties can be remarkably improved. The higher the annealing temperature is, the higher the magnetic induction and the lower the iron loss in ultra-thin silicon steel is.

Influence of nitrogen implantation into the buried oxide on the radiation hardness of silicon-on-insulator wafers

In order to improve the total-dose radiation hardness of the buried oxide of separation by implanted oxygen silicon- on-insulator wafers, nitrogen ions were implanted into the buried oxide with a dose of 1016 cm-2, and subsequent annealing was performed at 1100 ℃. The effect of annealing time on the radiation hardness of the nitrogen implanted wafers has been studied by the high frequency capacitance-voltage technique. The results suggest that the improvement of the radiation hardness of the wafers can be achieved through a shorter time annealing after nitrogen implantation. The nitrogen-implanted sample with the shortest annealing time 0.5 h shows the highest tolerance to total-dose radiation. In particular, for the 1.0 and 1.5 h annealing samples, both total dose responses were unusual. After 300-krad（Si） irradiation, both the shifts of capacitance-voltage curve reached a maximum, respectively, and then decreased with increasing total dose. In addition, the wafers were analysed by the Fourier transform infrared spectroscopy technique, and some useful results have been obtained.

Stability Behaviour of Monolayer Tetraether Lipids on the Amino-Silanised Silicon Wafer: Comparative Study between Langmuir-Blodgett Monolayers with Self-Assembled Monolayers

This study investigated the stability behaviour of molecular monolayer symmetric chemically modified tetraether lipids caldarchaeol-PO4 on the amino-silanised silicon wafer using Langmuir-Blodgett films, Self Assembling Monolayers (SAMs), ellipsometry, and atomic force microscopy (AFM). The monolayers of caldarchaeol-PO4 were stable on the solid surface amino-silanised silicon wafer. The organizations of molecular monolayers caldarchaeol-PO4 by Langmuir-Blodgett method and SAMs have been analyzed. The surface of pressure in Langmuir-Blodgett processing is carried out monolayers caldarchaeol-PO4 more flat island inhomogeneous. Another method of monolayers caldarchaeol-PO4 by SAMs is showed a large flat domain. Monolayers caldarchaeol-PO4 by Langmuir-Blodgett method seems to be stable and chemically resistant after washing with organic solvent and an additional treatment ultrasonification with various thickness lipids arround 2 nm to 6 nm. Conversely, monolayer caldarchaeol-PO4 by SAMs appears fewer than monolayers caldarchaeol-PO4 by Langmuir-Blodgett method, the thickness of various from 1 nm to 3 nm.

Microstructure evolution and passivation quality of hydrogenated amorphous silicon oxide(a-SiOx:H) on〈100〉- and 〈111〉-orientated c-Si wafers

Hydrogenated amorphous silicon oxide(a-SiOx:H) is an attractive passivation material to suppress epitaxial growth and reduce the parasitic absorption loss in silicon heterojunction(SHJ) solar cells. In this paper, a-SiOx:H layers on different orientated c-Si substrates are fabricated. An optimal effective lifetime(τ(eff)) of 4743 μs and corresponding implied opencircuit voltage(iV(oc)) of 724 mV are obtained on〈100〉-orientated c-Si wafers. While τ(eff) of 2429 μs and iV_(oc) of 699 mV are achieved on 111-orientated substrate. The FTIR and XPS results indicate that the a-SiOx:H network consists of SiOx(Si-rich), Si–OH, Si–O–SiHx, SiO2 ≡ Si–Si, and O3 ≡ Si–Si. A passivation evolution mechanism is proposed to explain the different passivation results on different c-Si wafers. By modulating the a-SiOx:H layer, the planar silicon heterojunction solar cell can achieve an efficiency of 18.15%.

Finite Element Analysis for Grinding and Lapping of Wire-sawn Silicon Wafers

Silicon wafers are the most widely used substrates for semiconductors. The falling price of silicon wafers has created tremendous pressure on silicon wafer manufacturers to develop cost-effective manufacturing processes. A critical issue in wafer production is the waviness induced by wire sawing. If this waviness is not removed, it will affect wafer flatness and semiconductor performance. In practice, both lapping and grinding have been used to flatten wire-sawn wafers. Although grinding is not as effective as lapping in removing waviness, it has many other advantages over lapping (such as higher throughput, fully automatic, and more benign to environment) and has great potential to reduce manufacturing cost of silicon wafers. This paper presents a finite element analysis (FEA) study on grinding and lapping of wire-sawn silicon wafers. An FEA model is first developed to simulate the waviness deformation of wire-sawn wafers in grinding and lapping processes. It is then used to explain how the waviness is removed or reduced by lapping and grinding and why the effectiveness of grinding in removing waviness is different from that of lapping. Furthermore, the model is used to study the effects of various parameters including active-grinding-zone orientation, grinding force, waviness wavelength, and waviness height on the reduction and elimination of waviness. Finally, the results of pilot experiments to verify the model are discussed.

Surface Damage in Wire cut Silicon Wafers

The surface damage and the damage depth in wire-cut silicon wafers and inner-diameter (ID) cut silicon wafers were studied by means of thickness meter, scanning electron microscopy (SEM) and double crystal X-ray diffractometer. The results show that the surface of wire-cut silicon wafers is rougher than that of ID-cut silicon wafers and the surface damage in wire-cut silicon wafers is more serious than that in ID-cut silicon wafers, while the damage depth in wire-cut silicon wafers is smaller than that in ID-cut silicon wafers. The possible reasons for the generation of surface damage in wire-cut silicon wafers were also discussed.

Detailed Micro Raman Spectroscopy Analysis of Doped Silicon Thin Film Layers and Its Feasibility for Heterojunction Silicon Wafer Solar Cells

Hydrogenated doped silicon thin films deposited using RF (13.56 MHz) PECVD were studied in detail using micro Raman spectroscopy to investigate the impact of doping gas flow, film thickness, and substrate type on the film characteristics. In particular, by deconvoluting the micro Raman spectra into amorphous and crystalline components, qualitative and quantitative information such as bond angle disorder, bond length, film stress, and film crystallinity can be determined. By selecting the optimum doped silicon thin film deposition conditions, and combining our p-doped and n-doped silicon thin films in different heterojunction structures, we demonstrate both (i) an efficient field effect passivation and (ii) further improvement to c-Si/a-Si:H(i) interface defect density with observed improvement in implied open-circuit voltage VOC and minority carrier lifetimes across all injections levels of interest. In particular, the heterojunction structure (a-Si:H(p)/a-Si:H(i)/c-Si(n)/a-Si:H(i)/a-Si:H(p)) demonstrates a minority carrier lifetime of 2.4 ms at an injection level of 1015 cm-3, and a high implied open-circuit voltage of 725 mV. Simulation studies reveal a strong dependence of the interface defect density Dit on the heterojunction silicon wafer solar cell performance, affected by the deposition conditions of the overlying doped silicon thin film layers. Using our films, and a fitted Dit of 5 × 1010 cm-2·eV-1, we demonstrate that a solar cell efficiency of ~22.5% can be potentially achievable.