Low power consumption 4-channel variable optical attenuator array based on planar lightwave circuit technique

The power consumption of a variable optical attenuator（VOA） array based on a silica planar lightwave circuit was investigated. The thermal field profile of the device was optimized using the finite-element analysis. The simulation results showed that the power consumption reduces as the depth of the heat-insulating grooves is deeper, the up-cladding is thinner,the down-cladding is thicker, and the width of the cladding ridge is narrower. The materials component and thickness of the electrodes were also optimized to guarantee the driving voltage under 5 V. The power consumption was successfully reduced to as low as 155 mW at an attenuation of 30 dB in the experiment.

Low Power Consumption Distributed-Feedback Quantum Cascade Lasers Operating in Continuous-Wave Mode above 90℃ at λ～7.2μm

We report on the design and fabrication of λ-7.2μm distributed feedback quantum cascade lasers lot very high temperature cw operation and low electrical power consumption. The cw operation is reported above 90℃. For a 2-mm-long and 10-μm-wide laser coated with high-reflectivity on the rear facet, more than 170mW of output power is obtained at 20℃ with a threshold power consumption of 2.4 W, corresponding to 30mW with a threshold power consumption of 3.9 W at 90℃. Robust single-mode emission with a side-mode suppression ratio above 25 dB is continuously tunable by the heat sink temperature or injection current.

A vector inserting TPG for BIST design with low peak power consumption

A test pattern generator （TPG） which can highly reduce the peak power consumption during built-in self-test （BIST） application is proposed. The proposed TPG, called LPpe-TPG, consists of a linear feedback shift register （LFSR） and some control circuits. A procedure is presented firstly to make compare vectors between pseudorandom test patterns by adding some circuits to the original LFSR and secondly to insert some vectors between two successive pseudorandom test patterns according to the ordinal selection of every two bits of the compare vector. Then the changes between any successive test patterns of the test set generated by the LPpe-TPG are not more than twice. This leads to a decrease of the weighted switching activity （WSA） of the circuit under test （CUT） and therefore a reduction of the power consumption. Experimental results based on some ISCAS＇ 85 benchmark circuits show that the peak power consumption has been reduced by 25.25% to 64.46%. Also, the effectiveness of our approach to reduce the total and average power consumption is kept, without losing stuck-at fault coverage.

A Study of Efficient Power Consumption Wireless Communication Techniques/ Modules for Internet of Things (IoT) Applications

A study of wireless technologies for IoT applications in terms of power consumption has been presented in this paper. The study focuses on the importance of using low power wireless techniques and modules in IoT applications by introducing a comparative between different low power wireless communication techniques such as ZigBee, Low Power Wi-Fi, 6LowPAN, LPWA and their modules to conserve power and longing the life for the IoT network sensors. The approach of the study is in term of protocol used and the particular module that achieve that protocol. The candidate protocols are classified according to the range of connectivity between sensor nodes. For short ranges connectivity the candidate protocols are ZigBee, 6LoWPAN and low power Wi-Fi. For long connectivity the candidate is LoRaWAN protocol. The results of the study demonstrate that the choice of module for each protocol plays a vital role in battery life due to the difference of power consumption for each module/protocol. So, the evaluation of protocols with each other depends on the module used.

Study of a GaAs MESFET Model with Ultra-Low Power Consumption

A model of enhancement mode GaAs MESFET (EFET) for low power consumption and low noise applications has been obtained by using a small signal equivalent circuit whose component values are derived from the physical parameters and the bias condition. The dependence of the RF performance and DC power consumption on physical, material and technological parameters of EFET is also studied. The optimum range of the physical parameters is given which is useful for the design of active device of ultra low power consumption MMIC.

A hybrid storage technology for low power consumption and high I/O performance in an IPTV set-top box

A new method of prefetching data blocks from the NVCache to the page cache in main memory and cascading prefetching n-blocks from a hard disk to the NVCache together was proposed to reduce the spin-up frequency of a hybrid hard disk drive and thus enhance I/O performance.The proposed method consists of three steps:1) Analyzing the pattern of read requests in block units;2) Determining the number of blocks prefetched to the NVCache;3) Replacing blocks in the NVCache according to the block replacement policy.The proposed method can reduce the latency time of a hybrid hard disk and optimize the power consumption of an IPTV set-top box.Experimental results show that the proposed method provides better average response time compared to an existing adaptive multistream prefetching(AMP) method by 25.17%.It also reduces by 20.83% the average power consumption over that of the existing external caching in energy saving storage system(EXCES) method.

Low-noise,low-power-consumption seafloor vector magnetometer

The seafloor vector magnetometer is an effective tool for marine geomagnetic surveys and seafloor magnetotelluric(MT)detection.However,the noise,power consumption,cost,and volume characteristics of existing seafloor vector magnetometers are insufficient for practical use.Therefore,a low-noise,low-power-consumption seafloor vector magnetometer that can be used for data acquisition of deep-ocean geomagnetic vector components is developed and presented.A seafloor vector magnetometer mainly consists of a fluxgate sensor,data acquisition module,acoustic release module,glass sphere,frame,burn-wire release,and anchor.A new low-noise data acquisition module and a fluxgate sensor greatly reduce power consumption.Furthermore,compact size is achieved by integrating an acoustic telemetry module and replacing the acoustic release with an external burn-wire release.The new design and magnetometer characteristics reduce the volume of the instrument and the cost of hardware considerably,thereby improving the integrity and deployment efficiency of the equipment.Theoretically,it can operate for 90 days underwater at a maximum depth of 6000 m.The seafloor vector magnetometer was tested in the South China Sea and the Philippine Sea and obtained high-quality geomagnetic data.The deep-water environment facilitates magnetic field data measurements,and the magnetometer has an approximate noise level of 10 pT/rt(Hz)@1 Hz,a peak-to-peak value error of 0.2 nT,and approximate power consumption of 200 mW.The fluxgate sensor can measure the magnetic field in the lower frequency band and realize geomagnetic field measurements over prolonged periods.

SNMP代理中PowerPC 405EP的低功耗研究

采用嵌入式微型互联网技术的SNMP代理,对其自身的功耗有严格的要求。这样,就对其核心Cerf(tm)Cube 405EP提出了很高的要求。文中对PPC405EP处理器在本代理中的电源管理设置进行了探讨。

A low-power Rijndael S-Box based on pass transmission gate and composite field arithmetic

Using composite field arithmetic in Galois field can result in the compact Rijndael S-Box. However, the power con- sumption of this solution is too large to be used in resource-limited embedded systems. A full-custom hardware implementation of composite field S-Box is proposed for these targeted domains in this paper. The minimization of power consumption is implemented by optimizing the architecture of the composite field S-Box and using the pass transmission gate (PTG) to realize the logic functions of S-Box. Power simulations were performed using the netlist extracted from the layout. HSPICE simulation results indicated that the proposed S-Box achieves low power consumption of about 130 μW at 10 MHz using 0.25 μm/2.5 V technology, while the consumptions of the positive polarity reed-muller (PPRM) based S-Box and composite field S-Box based on the conventional CMOS logic style are about 240 μW and 420 μW, respectively. The simulations also showed that the presented S-Box obtains better low-voltage operating property, which is clearly relevant for applications like sensor nodes, smart cards and radio frequency identification (RFID) tags.

A Novel Ultra Low Power High Performance Atto-Ampere CMOS Current Mirror with Enhanced Bandwidth

A novel CMOS atto-ampere current mirror （AACM） is proposed which reaches the minimum yet reported current range of 0.4 aA. Operation of this circuit is based on the source voltage modulation instead of the conventionally used gate voltage modulation which interestingly prevents usage of commonly required voltage shifting in those circuits. The proposed circuit has a simple structure prohibiting large chip area consumption which consumes extremely low power of 1.5 μW. It is thus the best choice for ultra low power low voltage （ULPLV） applications. By using a very simple frequency compensation technique, its bandwidth is widened to 15.8 kHz. Simulation results in SMIC （Semiconductor Manufacturing International Corporation） 0.18 μm CMOS technology with Hspice are presented to demonstrate the validation of the proposed current mirror.

A Low Power and High Speed Viterbi Decoder Based on Deep Pipelined, Clock Blocking and Hazards Filtering

A high speed and low power Viterbi decoder architecture design based on deep pipelined, clock gating and toggle filtering has been presented in this paper. The Add-Compare-Select (ACS) and Trace Back (TB) units and its sub circuits of the decoder have been operated in deep pipelined manner to achieve high transmission rate. The Power dissipation analysis is also investigated and compared with the existing results. The techniques that have been employed in our low-power design are clock-gating and toggle filtering. The synthesized circuits are placed and routed in the standard cell design environment and implemented on a Xilinx XC2VP2fg256-6 FPGA device. Power estimation obtained through gate level simulations indicated that the proposed design reduces the power dissipation of an original Viterbi decoder design by 68.82% and a speed of 145 MHz is achieved.

Selection and Design of WSN Node Based on Solar Power in Facility Greenhouse

In this study, the green energy saving of greenhouse sensor node is de- signed to reduce the system power consumption and high efficiency. The green renewable solar energy resources are used as the energy source of nodes; the lowenergy consumed and cost effective MSP430 chip is used as the main control chip of the processor unit; the transmission frequency of the wireless transmission unit is 433 MHz, which has the characteristics of low power consumption, high signal strength, long transmission distance and small signal attenuation during the transmission; the power supply system unit is composed of monocrystalline silicon solar panel and high performance rechargeable lithium ion battery. The selection basis of each unit is clarified in detail, and optimization is performed by hardware circuit and software program to further reduce power consumption. The power consumption of the node is calculated by the experiment, and the charging conditions of the solar panel used in the node is tested. The results show that the system can achieve the setting target through the selection and design.

Resistive switching characteristic and uniformity of low-power HfO_x-based resistive random access memory with the BN insertion layer

In this letter,the Ta/HfO/BN/TiN resistive switching devices are fabricated and they exhibit low power consumption and high uniformity each.The reset current is reduced for the HfO/BN bilayer device compared with that for the Ta/HfO/TiN structure.Furthermore,the reset current decreases with increasing BN thickness.The HfOlayer is a dominating switching layer,while the low-permittivity and high-resistivity BN layer acts as a barrier of electrons injection into TiN electrode.The current conduction mechanism of low resistance state in the HfO/BN bilayer device is space-chargelimited current(SCLC),while it is Ohmic conduction in the HfOdevice.

Low-Power Design of Ethernet Data Transmission

For the reliability and power consumption issues of Ethernet data transmission based on the field programmable gate array （FPGA）, a low-power consumption design method is proposed, which is suitable for FPGA implementation. To reduce the dynamic power consumption of integrated circuit （IC） design, the proposed method adopts the dynamic control of the clock frequency. For most of the time, when the port is in the idle state or lower-rate state, users can reduce or even turn off the reading clock frequency and reduce the clock flip frequency in order to reduce the dynamic power consumption. When the receiving rate is high, the reading clock frequency will be improved timely to ensure that no data will lost. Simulated and verified by Modelsim, the proposed method can dynamically control the clock frequency, including the dynamic switching of high-speed and low-speed clock flip rates, or stop of the clock flip.

天文应用红外焦平面读出电路研究

成功设计了一款天文应用的640×512短波红外焦平面读出电路。由于红外天文观测具有极低背景辐射、光子通量低的特点,为了实现探测器的高信噪比,需要降低器件的暗电流和电路噪声。电路采用有效的功耗管理策略,在保证电路正常工作的前提下尽可能地降低电路功耗以减小电路辉光对器件暗电流的影响。同时,研究非破坏性读出的数字功能,实现了超长的积分时间和信号的多帧累积,并作为一种斜坡采样的策略有效地降低读出噪声。短波HgCdTe焦平面的测试结果符合理论设计预期,开启电路非破坏性读出功能,设置6 000 s的积分时间,当电路功耗调低至14.04 mW时暗电流为0.9 e-·pixel^(-1)·s^(-1)。读出噪声在两档增益下分别为50 e-(10 fF)和27 e-(5 fF),非线性度低于0.1%。

考虑超碳需求响应的综合能源系统低碳优化调度

西北地区新能源发展迅速,充分利用当地独有的光热资源优势,同时结合火电低碳化改造与新能源协同运行,有利于推动当地能源系统绿色低碳转型。为尽最大限度地提升系统的减碳能力,提出一种基于源荷协同降碳的超碳需求响应模型,将动态碳排放因子作为分时电价的惩罚因子,从而将源侧碳信号传递至荷侧,驱使用户侧进行低碳性状态转移。首先,在日前调度阶段,构建预调度-再调度两阶段调度运行机制,再调度根据预调度的系统状态信息进行超碳需求响应,来深度降低系统碳排量。其次,将光热电站引入综合能源系统,与风电场、碳捕集电厂协同运行,从而构建高比例新能源场景,来验证超碳需求响应在此场景下的减碳效益。最后,建立了基于超碳需求响应的预调度-再调度两阶段低碳调度模型。经算例仿真分析表明,所提源荷协同降碳的新思路能有效提高系统的减碳能力,深入挖掘系统的降碳空间,提升系统的经济效益。

Ultra-Low Power Designing for CMOS Sequential Circuits

Power consumption is the bottleneck of system performance. Power reduction has become an important issue in digital circuit design, especially for high performance portable devices (such as cell phones, PDAs, etc.). Many power reduction techniques have also been proposed from the system level down to the circuit level. High-speed computation has thus become the expected norm from the average user, instead of being the province of the few with access to a powerful mainframe. Power must be added to the portable unit, even when power is available in non-portable applications, the issue of low-power design is becoming critical. Thus, it is evident that methodologies for the design of high-throughput, low-power digital systems are needed. Techniques for low-power operation are shown in this paper, which use the lowest possible supply voltage coupled with architectural, logic style, circuit, and technology optimizations. The threshold vol-tages of the MTCMOS devices for both low and high Vth are constructed as the low threshold Vth is approximately 150 - 200 mv whereas the high threshold Vth is managed by varying the thickness of the oxide Tox. Hence we are using different threshold voltages with minimum voltages and hence considered this project as ultra-low power designing.

Ultra-Low Power Pipeline Structure Exploiting Noncritical Stage with Circuit-Level Timing Speculation

With the increase of the clock frequency and silicon integration, power aware computing has become a critical concern in the design of the embedded processor and system-on-chip （SoC）. Dynamic voltage scaling （DVS） is an effective method for low-power designs. However, traditional DVS methods have two deficiencies. First, they have a conservative safety margin which is not necessary for most of the time. Second, they are exclusively concerned with the critical stage and ignore the significant potential free slack time of the noncritical stage. These factors lead to a large amount of power waste. In this paper, a novel pipeline structure with ultra-low power consumption is proposed. It cuts off the safety margin and takes use of the noncritical stages at the same time. A prototype pipeline is designed in 0.13 μm technology and analyzed. The result shows that a large amount of energy can be saved by using this structure. Compared with the fixed voltage case, 50% of the energy can be saved, and with respect to the traditional adaptive voltage scaling design, 37.8% of the energy can be saved.

Re-understanding and Thinking about Environmental Impact of Coal-fired Power Plants under Ultra-low Emission

From the perspective of development background,concepts and related policies of ultra-low emission,according to work practice,some issues and difficulties that need to be paid attention to in the environmental impact assessment of ultra-low-emission thermal power projects were discussed from the aspects of evaluation criteria,evaluation grade and scope,pollution control technical lines,environmental benefit accounting,and total emission control,and corresponding recommendations were put forward.

基于NB-IoT的地下管廊环境监测系统设计

城市地下管廊内布设了大量的管线,如燃气管道、网络通讯线路、电力线路等,由于地下环境复杂多变,存在着气体泄漏、爆炸、火灾等安全风险。针对这些问题,提出一种基于窄带物联网技术(Narrow Band Internet of Things,NB-IoT)的地下管廊环境监测系统。该系统采用先进的传感器技术、NB-IoT技术、软件技术,系统主要分为数据采集模块、物联网云平台、远程监测系统三部分。数据采集模块以STM32作为主控单元连接各个传感器,采集温度、湿度、水位、可燃气体等数据,经过处理后利用NB-IoT网络上传到物联网云平台,远程监测系统调用物联网云平台的数据接口进行远程显示与预警。实验结果表明,系统在降低系统总体功耗的同时,能够实时、稳定地进行地下管廊环境监测,提前预防可能存在的风险。