In order to meet the needs of higher operation speed and lower energy consumption an optimized SHA-1 algorithm is proposed.It combines two methods loop-unfolding and pre-processing.In the process intermediate variable...In order to meet the needs of higher operation speed and lower energy consumption an optimized SHA-1 algorithm is proposed.It combines two methods loop-unfolding and pre-processing.In the process intermediate variables are introduced in the iterations and pre-calculated so that the original single-threading operation can perform in a multi-threading way.This optimized algorithm exploits parallelism to shorten the critical path for hash operations.And the cycles of the original algorithm are reduced from 80 to 41 which greatly improves the operation speed.Therefore the shortened iterations of the optimized design require a smaller amount of hardware resource thus achieving a lower energy consumption. The optimized algorithm is implemented on FPGA field programmable gate array .It can achieve a throughput rate of 1.2 Gbit /s with the maximum clock frequency of 91 MHz reaching a fair balance between operation speed and throughput rate.The simulation results show that compared with other optimized SHA-1 algorithms this algorithm obtains higher operation speed and throughput rate without compromising the security of the original SHA-1 algorithm.展开更多
基金The Project of Wireless Intelligence Terminal Inspection Services(No.6704000084)the Special Program of the NationalDevelopment and Reform Committee
文摘In order to meet the needs of higher operation speed and lower energy consumption an optimized SHA-1 algorithm is proposed.It combines two methods loop-unfolding and pre-processing.In the process intermediate variables are introduced in the iterations and pre-calculated so that the original single-threading operation can perform in a multi-threading way.This optimized algorithm exploits parallelism to shorten the critical path for hash operations.And the cycles of the original algorithm are reduced from 80 to 41 which greatly improves the operation speed.Therefore the shortened iterations of the optimized design require a smaller amount of hardware resource thus achieving a lower energy consumption. The optimized algorithm is implemented on FPGA field programmable gate array .It can achieve a throughput rate of 1.2 Gbit /s with the maximum clock frequency of 91 MHz reaching a fair balance between operation speed and throughput rate.The simulation results show that compared with other optimized SHA-1 algorithms this algorithm obtains higher operation speed and throughput rate without compromising the security of the original SHA-1 algorithm.
