A novel programmable gain amplifier（ PGA） based on a signal-summing topology is proposed. Different from conventional signal-summing variable gain amplifiers（ VGA）,a binary-weighted switching technique is employed...A novel programmable gain amplifier（ PGA） based on a signal-summing topology is proposed. Different from conventional signal-summing variable gain amplifiers（ VGA）,a binary-weighted switching technique is employed to vary the current-steering transistors＇ aspect ratio to change their transconductance, and hence, an accurate gain step size of 6dB is achieved. The constant-g_m biasing technique and the matching of the transistors and resistors ensures that the gain of the proposed topology is independent of the variation of process, voltage and temperature（ PVT）. P-well NMOS（ Nmetal oxide semiconductor） transistors are utilized to eliminate the influence of back-gate effect which will induce gain error.The source-degeneration technique ensures good linearity performance at a low gain. The proposed PGA is fabricated in a0.18 μm CMOS（ complementary metal oxide semiconductor）process. The measurement results show a variable gain ranging from 0 to24 dB with a step size of 6 dB and a maximum gain error of 0. 3dB. A constant 3dB bandwidth of 210 MHz is achieved at different gain settings. The measured output 3rd intercept point（OIP3） and minimum noise figure（ NF） are20. 9 dBm and 11.1 dB, respectively. The whole PGA has a compact layout of 0.068 mm^2. The total power consumption is4. 8 mW under a 1. 8 V supply voltage.展开更多
This paper presents a low-voltage low-power variable gain amplifier,which is applied in the automatic gain control loop of a super heterodyne receiver. Six stages are cascaded to provide an 81dB digitally controlled g...This paper presents a low-voltage low-power variable gain amplifier,which is applied in the automatic gain control loop of a super heterodyne receiver. Six stages are cascaded to provide an 81dB digitally controlled gain range in a 3dB step. The gain step error is less than 0.5dB. It operates at an intermediate frequency of 300kHz, and the power consumption is 1.35mW from a 1.8V supply. The prototype chip is implemented in a TSMC＇s 0.18μm 1P6M CMOS process and occupies approximately 0.24mm^2 . It is very suitable for portable wire- less communication systems. The measurement results agree well with the system requirements.展开更多
采用电压控制的伪电阻结构,设计了一款具有超低频下截止频率调节功能的带通可变增益放大器(VGA),由于该结构具有可调节超大的等效电阻和反馈电容使VGA的下截止频率可以调节。提出了一种改进的甲乙类运算跨导放大器(OTA)结构,采用新颖的...采用电压控制的伪电阻结构,设计了一款具有超低频下截止频率调节功能的带通可变增益放大器(VGA),由于该结构具有可调节超大的等效电阻和反馈电容使VGA的下截止频率可以调节。提出了一种改进的甲乙类运算跨导放大器(OTA)结构,采用新颖的浮动偏置设计,在满足高压摆率的条件下,有效提高共源共栅结构的电压输出范围。将伪电阻用于OTA的共模反馈,克服了阻性共模检测结构负载效应的问题。该VGA电路采用TSMC 0.18μm标准工艺设计和流片,测试结果表明,1.2 V电源电压下,其下截止频率调节范围为1.3~244 Hz,增益为49.2,44.2,39.2 d B,带宽为3.4,3.9,4.4 k Hz,消耗电流为3.9μA,共模抑制比达75.2 d B。展开更多
This paper presented an automatic gain control （AGC） circuit suitable for FM/cw ladar. The proposed architecture was based on two-stage variable gain amplifier （VGA） chain with a novel DC offset canceller circuit,...This paper presented an automatic gain control （AGC） circuit suitable for FM/cw ladar. The proposed architecture was based on two-stage variable gain amplifier （VGA） chain with a novel DC offset canceller circuit, which contained an improved Gilbert cell and a Gm-C feedback loop. To keep the VGA with a linearity in dB characteristic, an improved exponential gain control circuit was introduced. The AGC was implemented in 0.18 gm standard CMOS process. Simulation and measurement results verified that its gain ranged from -20 dB to 30 dB, and band- width ranged from 100 kHz to 10 MHz. Its power consumption was 19.8 mW under a voltage supply of 3.3 V.展开更多
A compact and reconfigurable low noise amplifier(LNA)is proposed by combining an input transistor,composite transistors with Darlington configuration as the amplification and output transistor,T-type structure composi...A compact and reconfigurable low noise amplifier(LNA)is proposed by combining an input transistor,composite transistors with Darlington configuration as the amplification and output transistor,T-type structure composite resistors instead of a simplex structure resistor,a shunt inductor feedback realized by a tunable active inductor(AI),a shunt inductor peaking technique realized by another tunable AI.The division and collaboration among different resistances in the T-type structure composite resistor realize simultaneously input impedance matching,output impedance matching and good noise performance;the shunt feedback and peaking technique using two tunable AIs not only extend frequency bandwidth and improve gain flatness,but also make the gain and frequency band can be tuned simultaneously by the external bias of tunable AIs;the Darlington configuration of composite transistors provides high gain;furthermore,the adoption of the small size AIs instead of large size passive spiral inductor,and the use of composite resistors make the LNA have a small size.The LNA is fabricated and verified by GaAs/InGaP hetero-junction bipolar transistor(HBT)process.The results show that at the frequency of 7 GHz,the gain S_(21)is maximum and up to 19 dB;the S_(21)can be tuned from 17 dB to 19 dB by tuning external bias of tunable AIs,that is,the tunable amount of S_(21)is 2 dB,and similarly at 8 GHz;the tunable range of 3 dB bandwidth is 1 GHz.In addition,the gain S_(21)flatness is better than 0.4 dB under frequency from 3.1 GHz to 10.6 GHz;the size of the LNA only has 760μm×1260μm(including PADs).Therefore,the proposed strategies in the paper provide a new solution to the design of small size and reconfigurable ultra-wideband(UWB)LNA and can be used further to adjust the variations of gain and bandwidth of radio frequency integrated circuits(RFICs)due to package,parasitic and the variation of fabrication process and temperature.展开更多
在宽带任意波发生器(AWG)研制中,一个重要的挑战来自宽带可变增益放大器(VGA)。作为设备的信号输出接口电路,VGA承担了输出信号放大、共模电压调节、驱动负载等重要功能,在很大程度上决定了设备的综合性能。设计了一款适用于宽带AWG的VG...在宽带任意波发生器(AWG)研制中,一个重要的挑战来自宽带可变增益放大器(VGA)。作为设备的信号输出接口电路,VGA承担了输出信号放大、共模电压调节、驱动负载等重要功能,在很大程度上决定了设备的综合性能。设计了一款适用于宽带AWG的VGA芯片,采用一种改进的数字增益调节架构,在兼顾带宽的同时,消除了模拟控制电压的影响,并确保了增益的单调性。芯片采用SiGe BiCMOS工艺实现,测试结果表明,芯片可以实现0.125~2倍的单调增益控制,最小增益步进约为0.125倍;在输入信号频率为4 GHz时的输出信号衰减为-2.83 d B。展开更多
This paper presents a wideband variable gain amplifier(VGA) featuring a decibel-linear gain control characteristic. The decibel-linear gain control function is realized using two VGA cells and a control signal convert...This paper presents a wideband variable gain amplifier(VGA) featuring a decibel-linear gain control characteristic. The decibel-linear gain control function is realized using two VGA cells and a control signal converter. The bandwidth is extended by using cascode architecture together with active inductive load. To achieve small parasitic and low area,direct current(DC) coupling is adopted in the circuit while a DC offset cancellation(DCOC) circuit is introduced to cancel the DC offset. Fabricated in a 0.18 μm complementary metal oxide semiconductor(CMOS) process, the chip occupies an area of 0.53 mm×0.48 mm(including pads) and draws a total current of 9 mA from a 1.8 V supply. The measurement results show that the gain of the VGA varies from-40 dB to 18 dB while the control voltage varies from 0 to 1.8 V, resulting in a total gain control range of 58 dB. The 3 dB bandwidth of the VGA is larger than 260 MHz at maximum gain.展开更多
This paper presents a novel approach for designing a reconfigurable variable gain amplifier（VGA） for the multi-mode multi-band receiver system RF front-end applications.The configuration,which is comprised of gain c...This paper presents a novel approach for designing a reconfigurable variable gain amplifier（VGA） for the multi-mode multi-band receiver system RF front-end applications.The configuration,which is comprised of gain circuits,control circuit,DC offset cancellation circuit and mode switch circuit is proposed to save die area and power consumption with the function of multi-mode and multi-band through reusing.The VGA is realized in 0.18μm CMOS technology with 1.8 V power supply voltage providing a gain tuning range from 5 to 87 dB when the control voltage varies from 0 to 1.8 V.The 3 dB bandwidth is about 80 MHz for all levels of control voltage（all gains）.Also,the DC offset cancellation circuit can effectively suppress DC offset to a value of less than 40 mV at the output regardless of the input.The overall power consumption is less than 3 mA,and die area is 705×100μm^2.展开更多
基金The National Natural Science Foundation of China(No.61306069)
文摘A novel programmable gain amplifier（ PGA） based on a signal-summing topology is proposed. Different from conventional signal-summing variable gain amplifiers（ VGA）,a binary-weighted switching technique is employed to vary the current-steering transistors＇ aspect ratio to change their transconductance, and hence, an accurate gain step size of 6dB is achieved. The constant-g_m biasing technique and the matching of the transistors and resistors ensures that the gain of the proposed topology is independent of the variation of process, voltage and temperature（ PVT）. P-well NMOS（ Nmetal oxide semiconductor） transistors are utilized to eliminate the influence of back-gate effect which will induce gain error.The source-degeneration technique ensures good linearity performance at a low gain. The proposed PGA is fabricated in a0.18 μm CMOS（ complementary metal oxide semiconductor）process. The measurement results show a variable gain ranging from 0 to24 dB with a step size of 6 dB and a maximum gain error of 0. 3dB. A constant 3dB bandwidth of 210 MHz is achieved at different gain settings. The measured output 3rd intercept point（OIP3） and minimum noise figure（ NF） are20. 9 dBm and 11.1 dB, respectively. The whole PGA has a compact layout of 0.068 mm^2. The total power consumption is4. 8 mW under a 1. 8 V supply voltage.
文摘This paper presents a low-voltage low-power variable gain amplifier,which is applied in the automatic gain control loop of a super heterodyne receiver. Six stages are cascaded to provide an 81dB digitally controlled gain range in a 3dB step. The gain step error is less than 0.5dB. It operates at an intermediate frequency of 300kHz, and the power consumption is 1.35mW from a 1.8V supply. The prototype chip is implemented in a TSMC＇s 0.18μm 1P6M CMOS process and occupies approximately 0.24mm^2 . It is very suitable for portable wire- less communication systems. The measurement results agree well with the system requirements.
文摘采用电压控制的伪电阻结构,设计了一款具有超低频下截止频率调节功能的带通可变增益放大器(VGA),由于该结构具有可调节超大的等效电阻和反馈电容使VGA的下截止频率可以调节。提出了一种改进的甲乙类运算跨导放大器(OTA)结构,采用新颖的浮动偏置设计,在满足高压摆率的条件下,有效提高共源共栅结构的电压输出范围。将伪电阻用于OTA的共模反馈,克服了阻性共模检测结构负载效应的问题。该VGA电路采用TSMC 0.18μm标准工艺设计和流片,测试结果表明,1.2 V电源电压下,其下截止频率调节范围为1.3~244 Hz,增益为49.2,44.2,39.2 d B,带宽为3.4,3.9,4.4 k Hz,消耗电流为3.9μA,共模抑制比达75.2 d B。
基金Supported by the National Science and Technology Major Project of the Ministry of Science and Technology of China(No.2012ZX03004008)
文摘This paper presented an automatic gain control （AGC） circuit suitable for FM/cw ladar. The proposed architecture was based on two-stage variable gain amplifier （VGA） chain with a novel DC offset canceller circuit, which contained an improved Gilbert cell and a Gm-C feedback loop. To keep the VGA with a linearity in dB characteristic, an improved exponential gain control circuit was introduced. The AGC was implemented in 0.18 gm standard CMOS process. Simulation and measurement results verified that its gain ranged from -20 dB to 30 dB, and band- width ranged from 100 kHz to 10 MHz. Its power consumption was 19.8 mW under a voltage supply of 3.3 V.
基金Supported by the National Natural Science Foundation of China(No.61774012,61574010)。
文摘A compact and reconfigurable low noise amplifier(LNA)is proposed by combining an input transistor,composite transistors with Darlington configuration as the amplification and output transistor,T-type structure composite resistors instead of a simplex structure resistor,a shunt inductor feedback realized by a tunable active inductor(AI),a shunt inductor peaking technique realized by another tunable AI.The division and collaboration among different resistances in the T-type structure composite resistor realize simultaneously input impedance matching,output impedance matching and good noise performance;the shunt feedback and peaking technique using two tunable AIs not only extend frequency bandwidth and improve gain flatness,but also make the gain and frequency band can be tuned simultaneously by the external bias of tunable AIs;the Darlington configuration of composite transistors provides high gain;furthermore,the adoption of the small size AIs instead of large size passive spiral inductor,and the use of composite resistors make the LNA have a small size.The LNA is fabricated and verified by GaAs/InGaP hetero-junction bipolar transistor(HBT)process.The results show that at the frequency of 7 GHz,the gain S_(21)is maximum and up to 19 dB;the S_(21)can be tuned from 17 dB to 19 dB by tuning external bias of tunable AIs,that is,the tunable amount of S_(21)is 2 dB,and similarly at 8 GHz;the tunable range of 3 dB bandwidth is 1 GHz.In addition,the gain S_(21)flatness is better than 0.4 dB under frequency from 3.1 GHz to 10.6 GHz;the size of the LNA only has 760μm×1260μm(including PADs).Therefore,the proposed strategies in the paper provide a new solution to the design of small size and reconfigurable ultra-wideband(UWB)LNA and can be used further to adjust the variations of gain and bandwidth of radio frequency integrated circuits(RFICs)due to package,parasitic and the variation of fabrication process and temperature.
文摘在宽带任意波发生器(AWG)研制中,一个重要的挑战来自宽带可变增益放大器(VGA)。作为设备的信号输出接口电路,VGA承担了输出信号放大、共模电压调节、驱动负载等重要功能,在很大程度上决定了设备的综合性能。设计了一款适用于宽带AWG的VGA芯片,采用一种改进的数字增益调节架构,在兼顾带宽的同时,消除了模拟控制电压的影响,并确保了增益的单调性。芯片采用SiGe BiCMOS工艺实现,测试结果表明,芯片可以实现0.125~2倍的单调增益控制,最小增益步进约为0.125倍;在输入信号频率为4 GHz时的输出信号衰减为-2.83 d B。
基金supported by the Natural Science Foundation and Special Major Basic Research Program of Hebei Province(18960202D)
文摘This paper presents a wideband variable gain amplifier(VGA) featuring a decibel-linear gain control characteristic. The decibel-linear gain control function is realized using two VGA cells and a control signal converter. The bandwidth is extended by using cascode architecture together with active inductive load. To achieve small parasitic and low area,direct current(DC) coupling is adopted in the circuit while a DC offset cancellation(DCOC) circuit is introduced to cancel the DC offset. Fabricated in a 0.18 μm complementary metal oxide semiconductor(CMOS) process, the chip occupies an area of 0.53 mm×0.48 mm(including pads) and draws a total current of 9 mA from a 1.8 V supply. The measurement results show that the gain of the VGA varies from-40 dB to 18 dB while the control voltage varies from 0 to 1.8 V, resulting in a total gain control range of 58 dB. The 3 dB bandwidth of the VGA is larger than 260 MHz at maximum gain.
基金Project supported by the Core Electronic Devices,High-End General Chips and Basic Software Produces Major Projects,China(No. 2009ZX01031-002-008).
文摘This paper presents a novel approach for designing a reconfigurable variable gain amplifier（VGA） for the multi-mode multi-band receiver system RF front-end applications.The configuration,which is comprised of gain circuits,control circuit,DC offset cancellation circuit and mode switch circuit is proposed to save die area and power consumption with the function of multi-mode and multi-band through reusing.The VGA is realized in 0.18μm CMOS technology with 1.8 V power supply voltage providing a gain tuning range from 5 to 87 dB when the control voltage varies from 0 to 1.8 V.The 3 dB bandwidth is about 80 MHz for all levels of control voltage（all gains）.Also,the DC offset cancellation circuit can effectively suppress DC offset to a value of less than 40 mV at the output regardless of the input.The overall power consumption is less than 3 mA,and die area is 705×100μm^2.
