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Low power and high speed explicit-pulsed double-edge triggered level converting flip-flop
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作者 戴燕云 Shen Jizhong 《High Technology Letters》 EI CAS 2010年第2期204-209,共6页
Variable supply voltage-clustered voltage scaling (VS-CVS) scheme can be very effective in reducing power consumption of CMOS circuits without degrading system performance. Level converting flip-flops (LCFFs) are ... Variable supply voltage-clustered voltage scaling (VS-CVS) scheme can be very effective in reducing power consumption of CMOS circuits without degrading system performance. Level converting flip-flops (LCFFs) are key elements in the CVS scheme. In this paper, a new explicit-pulsed double-edge triggered level converting flip-flop (nEP-DET-LCFF) is proposed, which employs double-edge triggering technique, dynamic structure, explicit pulse generator, conditional discharge technique and proper arrangement of stacked nMOS transistors to efficiently perform latching and level converting functions simultaneously. The proposed nEP-DET-LCFF combines merits of both conventional explicit-LCFFs and implicit-LCFFs. Simulation shows the proposed nEP-DET-LCFF has improvement of 19.2% -46% in delay, and 19.4% - 52.9% in power-delay product (PDP) as compared with the published LCFFs. 展开更多
关键词 level converter FLIP-FLOP low power variable supply voltage
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