Spatial and temporal variation process of seabed dynamic response induced by the internal solitary wave

Internal solitary wave(ISW)is often accompanied by huge energy transport,which will change the pore water pressure in the seabed.Based on the two-dimensional Biot consolidation theory,the excess pore water pressure in seabed was simulated,and the spatiotemporal distribution characteristics of excess pore water pressure was studied.As the parameters of both ISW and seabed can affect the excess pore water pressure,the distribution of pore water pressure showed both dissipation and phase lag.And parametric studies were done on these two phenomena.Due to influenced by the phase lag of excess pore water pressure,the penetration depth under the site of northern South China Sea with total water depth 327 m,induced by typical internal solitary wave increased by 26.19%,53.27%and 149.86%from T_(0)to T_(0.5)in sand silt,clayey silt and fine sand seabed,respectively.That means the effect of ISW on seabed will be underestimated if we only take into accout the penetration depth under ISW trough,especially for fine sand seabed.In addition,the concept of“amplitude-depth ratio”had been introduced to describe the influence of ISW on seabed dynamic response in the actual marine environment.In present study,it is negatively correlated with the excess pore water pressure,and an ISW with smaller amplitude-depth ratio can wide the range of lateral impacts.Our study results help understand the seabed damage induced by the interaction between ISW and seabed.

Stochastic Analysis of Interconnect Delay in the Presence of Process Variations

Process variations can reduce the accuracy in estimation of interconnect performance. This work presents a process variation based stochastic model and proposes an effective analytical method to estimate interconnect delay. The technique decouples the stochastic interconnect segments by an improved decoupling method. Combined with a polynomial chaos expression （PCE）, this paper applies the stochastic Galerkin method （SGM） to analyze the system response. A finite representation of interconnect delay is then obtained with the complex approximation method and the bisection method. Results from the analysis match well with those from SPICE. Moreover, the method shows good computational efficiency, as the running time is much less than the SPICE simulation＇s.

The study of lithographic variation in resistive random access memory

Reducing the process variation is a significant concern for resistive random access memory(RRAM).Due to its ultrahigh integration density,RRAM arrays are prone to lithographic variation during the lithography process,introducing electrical variation among different RRAM devices.In this work,an optical physical verification methodology for the RRAM array is developed,and the effects of different layout parameters on important electrical characteristics are systematically investigated.The results indicate that the RRAM devices can be categorized into three clusters according to their locations and lithography environments.The read resistance is more sensitive to the locations in the array(~30%)than SET/RESET voltage(<10%).The increase in the RRAM device length and the application of the optical proximity correction technique can help to reduce the variation to less than 10%,whereas it reduces RRAM read resistance by 4×,resulting in a higher power and area consumption.As such,we provide design guidelines to minimize the electrical variation of RRAM arrays due to the lithography process.

Curvature Compensated CMOS Bandgap Reference with Novel Process Variation Calibration Technique

A lowtemperature coefficient（ TC） bandgap reference（ BGR） with novel process variation calibration technique is proposed in this paper. This proposed calibration technique compensating both TC and output value of BGR achieves fine adjustment step towards the reference voltage,while keeping optimal TC by utilizing large resistance to help layout match. The high-order curvature compensation realized by poly and p-diffusion resistors is introduced into the design to guarantee the temperature characteristic. Implemented in 180 nm technology,the proposed BGR has been simulated to have a power supply rejection ratio（ PSRR） of 91 dB@100 Hz. The calibration technique covers output voltage scope of 0. 49 V-0. 56 Vwith TC of 9. 45 × 10^（-6）/℃-9. 56 × 10^（-6）/℃ over the temperature range of-40 ℃-120 ℃. The designed BGR provides a reference voltage of 500 mV,with measured TC of 10. 1 × 10^（-6）/℃.

Improved Quality Prediction Model for Multistage Machining Process Based on Geometric Constraint Equation

Product variation reduction is critical to improve process efficiency and product quality, especially for multistage machining process（MMP）. However, due to the variation accumulation and propagation, it becomes quite difficult to predict and reduce product variation for MMP. While the method of statistical process control can be used to control product quality, it is used mainly to monitor the process change rather than to analyze the cause of product variation. In this paper, based on a differential description of the contact kinematics of locators and part surfaces, and the geometric constraints equation defined by the locating scheme, an improved analytical variation propagation model for MMP is presented. In which the influence of both locator position and machining error on part quality is considered while, in traditional model, it usually focuses on datum error and fixture error. Coordinate transformation theory is used to reflect the generation and transmission laws of error in the establishment of the model. The concept of deviation matrix is heavily applied to establish an explicit mapping between the geometric deviation of part and the process error sources. In each machining stage, the part deviation is formulized as three separated components corresponding to three different kinds of error sources, which can be further applied to fault identification and design optimization for complicated machining process. An example part for MMP is given out to validate the effectiveness of the methodology. The experiment results show that the model prediction and the actual measurement match well. This paper provides a method to predict part deviation under the influence of fixture error, datum error and machining error, and it enriches the way of quality prediction for MMP.

A statistical RCL interconnect delay model taking account of process variations

As the feature size of the CMOS integrated circuit continues to shrink, process variations have become a key factor affecting the interconnect performance. Based on the equivalent Elmore model and the use of the polynomial chaos theory and the Galerkin method, we propose a linear statistical RCL interconnect delay model, taking into account process variations by successive application of the linear approximation method. Based on a variety of nano-CMOS process parameters, HSPICE simulation results show that the maximum error of the proposed model is less than 3.5%. The proposed model is simple, of high precision, and can be used in the analysis and design of nanometer integrated circuit interconnect systems.

Effects of PHC on Water Quality of Jiaozhou BayⅢ.Land Transfer Process

Based on investigation data of PHC content in Jiaozhou Bay,China from 1979 to 1983,the seasonal variations of PHC content and monthly changes of precipitation in Jiaozhou Bay were analyzed. The results showed that seen from the spatial and temporal distribution,the seasonal variation of PHC content in the surface water of Jiaozhou Bay was based on the flow of the rivers as well as human activity,so PHC content in the rivers depended on the flow of the rivers and human activity,and the peaks and valleys of PHC content appeared in various seasons. The seasonal variation of PHC content in the surface water of Jiaozhou Bay depended on its land transfer process. The land transfer process was composed of use of PHC by mankind,deposition of PHC in soil and on the earth＇s surface,and transportation of PHC to offshore waters of sea by rivers and surface runoff. PHC content depended on mankind during the process from being used to entering soil and on precipitation during the process of being transported from soil to ocean.

A Numerical Research on the Influences of the Diurnal Variation of Solar Radiation on the Medium-Range Weather Processes

In this paper, we use a spectral model for the medium-range numerical weather forecast to discuss the impact of the diurnal variation of solar radiation on the medium-range weather processes. Under the tests of two typical winter and summer cases, we find that the influences of the diurnal variation of solar radiation on summer weather are really important, especially on its rainfall, surface heat transport and 500 hPa height field. On winter weather, however, the influences are very weak.

Statistical Elmore delay of RC interconnect tree

As feature size keeps scaling down, process variations can dramatically reduce the accuracy in the estimation of interconnect performance. This paper proposes a statistical Elmore delay model for RC interconnect tree in the presence of process variations. The suggested method translates the process variations into parasitic parameter extraction and statistical Elmore delay evaluation. Analytical expressions of mean and standard deviation of interconnect delay can be obtained in a given t^uctuation range of interconnect geometric parameters. Experimental results demonstrate that the approach matches well with Monte Carlo simulations. The errors of proposed mean and standard deviation are less than 1% and 7%, respectively. Simulations prove that our model is efficient and accurate.

Comparative Performance Evaluation of Large FPGAs with CNFET-and CMOS-based Switches in Nanoscale

Routing resources are the major bottlenecks in improving the performance and power consumption of the current FPGAs. Recently reported researches have shown that carbon nanotube field effect transistors(CNFETs) have considerable potentials for improving the delay and power consumption of the modern FPGAs. In this paper, hybrid CNFET-CMOS architecture is presented for FPGAs and then this architecture is evaluated to be used in modern FPGAs. In addition, we have designed and parameterized the CNFET-based FPGA switches and calibrated them for being utilized in FPGAs at 45 nm, 22 nm and 16 nm technology nodes.Simulation results show that the CNFET-based FPGA switches improve the current FPGAs in terms of performance, power consumption and immunity to process and temperature variations. Simulation results and analyses also demonstrate that the performance of the FPGAs is improved about 30%, on average and the average and leakage power consumptions are reduced more than 6% and 98% respectively when the CNFET switches are used instead of MOSFET FPGA switches. Moreover, this technique leads to more than 20.31%smaller area. It is worth mentioning that the advantages of CNFET-based FPGAs are more considerable when the size of FPGAs grows and also when the technology node becomes smaller.

Symbolic Macromodeling for Statistical Simulation of Operational Amplifiers

Symbolic circuit simulator is traditionally applied to the small-signal analysis of analog circuits. This paper establishes a symbolic behavioral macromodeling method applicable to both small-signal and large-signal analysis of general two-stage operational amplifiers （op-amps）. The proposed method creates a two-pole parametric macromodel whose parameters are analytical functions of the circuit element parameters generated by a symbolic circuit simulator. A moment matching technique is used in deriving the analytical model parameter. The created parametric behavioral model can be used for op-amps performance simulation in both frequency and time domains. In particular, the parametric models are highly suited for fast statistical simulation of op-amps in the time-domain. Experiment results show that the statistical distributions of the op-amp slew and settling time characterized by the proposed model agree well with the transistor-level results in addition to achieving significant speedup.

一种新的统计模型提取方法

随着半导体技术的不断发展,芯片制程的特征尺寸已由28nm、14nm、向7nm、5nm及以下逐步减小,工艺波动对器件性能的影响也变得越来越明显,因此统计模型对于EDA软件开发,IC设计(IC-Design)显得愈加重要。尤其对于系统波动和随机波动带来的器件性能的变化进行了统计分析和参数提取,在良率分析中有着至关重要的作用;为此,统计模型的提取,特别是一些非线性特性的分析应用,需要更多的研究。本文提出一种新的统计模型提取方法-主元向后传递(backward propagation of principal component,BPPC)。其相较传统方法,具有高效易用、极大地降低了统计模型的提取难度,并实现了统计模型从线性到非线性的扩展等特点。本文将从理论分析、算法流程、非线性扩展、应用实例等几部分对BPPC进行具体介绍。

Temperature and Process Variations Aware Dual Threshold Voltage Footed Domino Circuits Leakage Management

Considering the effect of temperature and process variations, the inputs and clock signals combination sleep state dependent leakage current characteristics is analyzed and the optimal sleep state is examined in sub-65nm dual threshold voltage （V1） footed domino circuits. HSPICE simulations based on 65nm and 45nm BSIM4 models show that the proposed CLIL state （the clock signal and inputs are all low） is the optimal state to reduce the leakage current of the high fan-in footed domino circuits at high temperature and almost all footed domino circuits at room temperature, as compared to the conventional CHIL state （the clock signal is high and inputs are all low） and the CHIH state （the clock signal and inputs are all high）. Further, the influence of the process variations on the leakage current characteristics of the dual V1 footed domino circuits is evaluated. At last, temperature and process variation aware new low leakage current setup guidelines are provided.

The impact of process variations on input impedance and mitigation using a circuit technique in FinFET-based LNA

The effect of process variations of a FinFET-based low noise amplifier （LNA） are mitigated by using the device in an independently driven mode, i.e. an independently driven double gate （IDDG） FinFET. A 45 nm gate length IDDG FinFET-based cascoded LNA, operating at 5 GHz, is designed and studied to assess the impact of process variation on the LNA performance metrics such as input impedance, gain and noise figure. Four geometrical parameters, gate length, channel width, gate oxide thickness and fin width, and one non-geometrical parameter, channel doping concentration, are considered in the study. The effect of these variations on the input impedance （the desired value is 50 f2 purely real） of the LNA is compensated by the second gate bias of the IDDG FinFET.

Fast Level-Set-Based Inverse Lithography Algorithm for Process Robustness Improvement and Its Application

Inverse lithography technology （ILT） is one of the promising resolution enhancement techniques （RETs）, as the advanced integrated circuits （IC） technology nodes still use the 193 nm light source. Among all the algorithms for ILT, the level-set-based ILT （LSB-ILT） is a feasible choice with good production result in practice. However, existing ILT algorithms optimize masks at nominal process condition without giving sufficient attention to the process variations, and thus the optimized masks show poor performance with focus and dose variations. In this paper, we put forward a new LSB-ILT algorithm for process robustness improvement with fast convergence. In order to account for the process variations in the optimization, we adopt a new form of the cost function by adding the objective function of process variation band （PV band） to the nominal cost. We also adopt the hybrid conjugate gradient （CG） method to reduce the runtime of the algorithm. We perform experiments on ICCAD 2013 benchmarks and the results show that our algorithm outperforms the top two winners of the ICCAD 2013 contest by 6.5%. We also adopt the attenuated phase shift mask （att-PSM） in the experiment with test cases from industry. The results show that our new algorithm has a fast convergence speed and reduces the process manufacturability index （PMI） by 38.77% compared with the LSB-ILT algorithm without the consideration of PV band.

Reliable buffered clock tree routing algorithm with process variation tolerance

When IC technology is scaled into the very deep sub-micron regime, the optical proximity effects （OPE） turn into noticeable in optical lithography. Consequently, clock skew becomes more and more susceptible to process variations, such as OPE. In this paper, we propose a new buffered clock tree routing algorithm to prevent the influence of OPE and process variations to clock skew. Based on the concept of BSF （branch sensitivity factor）, our algorithm manages to reduce the skew sensitivity of the clock tree in the topology generation. The worst case skew due to the wire width change has been estimated, and proper buffers are inserted to avoid large capacitance load. Experimental results show that our algorithm can produce a more reliable, processinsensitive clock tree, and control clock skews in their permissible range evidently.

Machining Error Control by Integrating Multivariate Statistical Process Control and Stream of Variations Methodology

For aircraft manufacturing industries, the analyses and prediction of part machining error during machining process are very important to control and improve part machining quality. In order to effectively control machining error, the method of integrating multivariate statistical process control （MSPC） and stream of variations （SoV） is proposed. Firstly, machining error is modeled by multi-operation approaches for part machining process. SoV is adopted to establish the mathematic model of the relationship between the error of upstream operations and the error of downstream operations. Here error sources not only include the influence of upstream operations but also include many of other error sources. The standard model and the predicted model about SoV are built respectively by whether the operation is done or not to satisfy different requests during part machining process. Secondly, the method of one-step ahead forecast error （OSFE） is used to eliminate autocorrelativity of the sample data from the SoV model, and the T2 control chart in MSPC is built to realize machining error detection according to the data characteristics of the above error model, which can judge whether the operation is out of control or not. If it is, then feedback is sent to the operations. The error model is modified by adjusting the operation out of control, and continually it is used to monitor operations. Finally, a machining instance containing two operations demonstrates the effectiveness of the machining error control method presented in this paper.

A fast-settling frequency-presetting PLL frequency synthesizer with process variation compensation and spur reduction

This paper proposes a fast-settling frequency-presetting PLL frequency synthesizer. A mixedsignal VCO and a digital processor are developed to accurately preset the frequency of VCO and greatly reduce the settling time. An auxiliary tuning loop is introduced in order to reduce reference spur caused by leakage current. The digital processor can automatically compensate presetting frequency variation with process and temperature, and control the operation of the auxiliary tuning loop. A 1.2 GHz integer-N synthesizer with 1 MHz reference input was implemented in a 0.18 μm process. The measured results demonstrate that the typical settling time of the synthesizer is less than 3 μs, and the phase noise is –108 dBc/Hz@1MHz. The reference spur is –52 dBc.

Fast statistical delay evaluation of RC interconnect in the presence of process variations

Fast statistical methods of interconnect delay and slew in the presence of process fluctuations are proposed. Using an optimized quadratic model to describe the effects of process variations, the proposed method enables closedform expressions of interconnect delay and slew for the given variations in relevant process parameters. Simulation results show that the method, which has a statistical characteristic similar to traditional methodology, is more efficient compared to HSPICE-based Monte Carlo simulations and traditional methodology.

Analysis and impact of process variability on performance of junctionless double gate VeSFET

This paper presents an in-depth analysis of junctionless double gate vertical slit FET（JLDG VeSFET）device under process variability.It has been observed that junctionless FETs（JLDG VeSFET） are significantly less sensitive to many process parameter variations due to their inherent device structure and geometric properties.Sensitivity analysis reveals that the slit width,oxide thickness,radius of the device,gate length and channel doping concentration imperceptibly affect the device performance of JLDG VeSFET in terms of variation in threshold voltage,on current,off current and subthreshold slope（Ssub） as compared to its junction based counterpart i.e.MOSFET,because various short channel effects are well controlled in this device.The maximum variation in off current for JLDG VeSFET due to variation in different devices parameters is 5.6% whereas this variation is 38.8% for the MOS junction based device.However,variation in doping concentration in the channel region displays a small deviation in the threshold voltage and on current characteristics of the MOSFET device as compared to JL DG VeSFET.